74AC299SJ

74AC299SJ Datasheet

74AC299, 74ACT299 8-Input Universal Shift/Storage Register with Common Parallel I/O Pins

Part	Datasheet
74AC299SJ	74AC299SJ (pdf)

Related Parts	Information
74AC299MTCX	74AC299MTCX
74AC299SCX	74AC299SCX
74AC299MTC	74AC299MTC
74AC299SC	74AC299SC
74AC299PC	74AC299PC
74AC299SJX	74AC299SJX

PDF Datasheet Preview
74AC299, 74ACT299 8-Input Universal Shift/Storage Register with Common Parallel I/O Pins January 2008 74AC299, 74ACT299 8-Input Universal Shift/Storage Register with Common Parallel I/O Pins • ICC and IOZ reduced by 50% • Common parallel I/O for reduced pin count • Additional serial inputs and outputs for expansion • Four operating modes shift left, shift right, load and store • 3-STATE outputs for bus-oriented applications • Outputs source/sink 24mA • ACT299 has TTL-compatible inputs The AC/ACT299 is an 8-bit universal shift/storage register with 3-STATE outputs. Four modes of operation are possible hold store , shift left, shift right and load data. The parallel load inputs and flip-flop outputs are multiplexed to reduce the total number of package pins. Additional outputs are provided for flip-flops Q0, Q7 to allow easy serial cascading. A separate active LOW Master Reset is used to reset the register. Ordering Information Package Order Number Package Description 74AC299SC 74AC299SJ 74AC299MTC 74AC299PC M20B M20D MTC20 N20A 20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide 74ACT299SC 74ACT299MTC M20B MTC20 20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 20-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide 74ACT299PC N20A 20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. All packages are lead free per JEDEC J-STD-020B standard. 74AC299, 74ACT299 8-Input Universal Shift/Storage Register with Common Parallel I/O Pins Connection Diagram Logic Symbols IEEE/IEC Pin Description Pin Names Clock Pulse Input DS0 DS7 S0, S1 MR Serial Data Input for Right Shift Serial Data Input for Left Shift Mode Select Inputs Asynchronous Master Reset OE1, OE2 3-STATE Output Enable Inputs Parallel Data Inputs or 3-STATE Parallel Outputs Q0, Q7 Serial Outputs Functional Description The AC/ACT299 contains eight edge-triggered D-type flip-flops and the interstage logic necessary to perform synchronous shift left, shift right, parallel load and hold operations. The type of operation is determined by S0 and S1, as shown in the Truth Table. All flip-flop outputs are brought out through 3-STATE buffers to separate I/O pins that also serve as data inputs in the parallel load mode. Q0 and Q7 are also brought out on other pins for expansion in serial shifting of longer words. A LOW signal on MR overrides the Select and CP inputs and resets the flip-flops. All other state changes are initiated by the rising edge of the clock. Inputs can change when the clock is in either state provided only that the recommended setup and hold times, relative to the rising edge of CP, are observed. A HIGH signal on either OE1 or OE2 disables the 3-STATE buffers and puts the I/O pins in the high impedance state. In this condition the shift, hold, load and reset operations can still occur. The 3-STATE buffers are also disabled by HIGH signals on both S0 and S1 in preparation for a parallel load operation. Truth Table Inputs Response MR S1 S0 CP L X Asynchronous Reset = LOW Parallel Load I/On Qn Shift Right DS0 Q0, Q0 Q1, etc. Shift Left, DS7 Q7, Q7 Q6, etc. H L X Hold H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH Transition 1988 Fairchild Semiconductor Corporation 74AC299, 74ACT299 8-Input Universal Shift/Storage Register with Common Parallel I/O Pins Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 1988 Fairchild Semiconductor Corporation 74AC299, 74ACT299 8-Input Universal Shift/Storage Register with Common Parallel I/O Pins Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Parameter VCC IIK

PDF Datasheet Preview

74AC299, 74ACT299 8-Input Universal Shift/Storage Register with Common Parallel I/O Pins

January 2008
74AC299, 74ACT299 8-Input Universal Shift/Storage Register with Common Parallel I/O Pins
• ICC and IOZ reduced by 50%
• Common parallel I/O for reduced pin count
• Additional serial inputs and outputs for expansion
• Four operating modes shift left, shift right, load
and store
• 3-STATE outputs for bus-oriented applications
• Outputs source/sink 24mA
• ACT299 has TTL-compatible inputs

The AC/ACT299 is an 8-bit universal shift/storage register with 3-STATE outputs. Four modes of operation are possible hold store , shift left, shift right and load data. The parallel load inputs and flip-flop outputs are multiplexed to reduce the total number of package pins. Additional outputs are provided for flip-flops Q0, Q7 to allow easy serial cascading. A separate active LOW Master Reset is used to reset the register.
Ordering Information

Package Order Number

Package Description
74AC299SC 74AC299SJ 74AC299MTC
74AC299PC

M20B M20D MTC20

N20A
20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
74ACT299SC 74ACT299MTC

M20B MTC20
20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide
20-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide
74ACT299PC

N20A 20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.

All packages are lead free per JEDEC J-STD-020B standard.
74AC299, 74ACT299 8-Input Universal Shift/Storage Register with Common Parallel I/O Pins

Connection Diagram

Logic Symbols

IEEE/IEC

Pin Description

Pin Names

Clock Pulse Input

DS0 DS7 S0, S1 MR

Serial Data Input for Right Shift Serial Data Input for Left Shift Mode Select Inputs Asynchronous Master Reset

OE1, OE2
3-STATE Output Enable Inputs

Parallel Data Inputs or 3-STATE Parallel Outputs

Q0, Q7

Serial Outputs

Functional Description

The AC/ACT299 contains eight edge-triggered D-type flip-flops and the interstage logic necessary to perform synchronous shift left, shift right, parallel load and hold operations. The type of operation is determined by S0 and S1, as shown in the Truth Table. All flip-flop outputs are brought out through 3-STATE buffers to separate I/O pins that also serve as data inputs in the parallel load mode. Q0 and Q7 are also brought out on other pins for expansion in serial shifting of longer words.

A LOW signal on MR overrides the Select and CP inputs and resets the flip-flops. All other state changes are initiated by the rising edge of the clock. Inputs can change when the clock is in either state provided only that the recommended setup and hold times, relative to the rising edge of CP, are observed.

A HIGH signal on either OE1 or OE2 disables the 3-STATE buffers and puts the I/O pins in the high impedance state. In this condition the shift, hold, load and reset operations can still occur. The 3-STATE buffers are also disabled by HIGH signals on both S0 and S1 in preparation for a parallel load operation.

Truth Table

Inputs

Response

MR S1 S0 CP

L X Asynchronous Reset = LOW

Parallel Load I/On Qn

Shift Right DS0 Q0, Q0 Q1, etc.

Shift Left, DS7 Q7, Q7 Q6, etc.

H L X Hold

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial
= LOW-to-HIGH Transition
1988 Fairchild Semiconductor Corporation
74AC299, 74ACT299 8-Input Universal Shift/Storage Register with Common Parallel I/O Pins

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
1988 Fairchild Semiconductor Corporation
74AC299, 74ACT299 8-Input Universal Shift/Storage Register with Common Parallel I/O Pins

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only.

Parameter

VCC IIK

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived 74AC299SJ Datasheet file may be downloaded here without warranties.

Datasheet ID: 74AC299SJ 513096