74AC273SC

74AC273SC Datasheet

74AC273, 74ACT273 Octal D-Type Flip-Flop

Part	Datasheet
74AC273SC	74AC273SC (pdf)

Related Parts	Information
74AC273SCX	74AC273SCX
74AC273SJ	74AC273SJ
74AC273SJX	74AC273SJX
74AC273PC	74AC273PC
74AC273MTC	74AC273MTC
74AC273MTCX	74AC273MTCX

PDF Datasheet Preview
74AC273, 74ACT273 Octal D-Type Flip-Flop January 2008 74AC273, 74ACT273 Octal D-Type Flip-Flop • Ideal buffer for microprocessor or memory • Eight edge-triggered D-type flip-flops • Buffered common clock • Buffered, asynchronous master reset • See 377 for clock enable version • See 373 for transparent latch version • See 374 for 3-STATE version • Outputs source/sink 24mA • 74ACT273 has TTL-compatible inputs The AC273 and ACT273 have eight edge-triggered D-type flip-flops with individual D-type inputs and Q outputs. The common buffered Clock CP and Master Reset MR input load and reset clear all flip-flops simultaneously. The register is fully edge-triggered. The state of each D-type input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flipflop's Q output. All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR input. The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements. Ordering Information Order Number Package Number Package Description 74AC273SC 74AC273SJ 74AC273MTC 74AC273PC 74ACT273SC 74ACT273SJ 74ACT273MTC M20B M20D MTC20 N20A M20B M20D MTC20 20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide 20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. All packages are lead free per JEDEC J-STD-020B standard. 74AC273, 74ACT273 Octal D-Type Flip-Flop Connection Diagram Logic Symbols IEEE/IEC Pin Description Pin Names MR CP Description Data Inputs Master Reset Clock Pulse Input Data Outputs Logic Diagram Mode Select-Function Table Operating Mode Reset Clear Load ‘1' Load ‘0' Inputs MR CP Dn LXX Outputs Qn L H L H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH Transition Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 1988 Fairchild Semiconductor Corporation 74AC273, 74ACT273 Octal D-Type Flip-Flop Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Parameter VCC IIK VI IOK VO IO ICC or IGND TSTG TJ Supply Voltage DC Input Diode Current VI = VI = VCC + DC Input Voltage DC Output Diode Current VO = VO = VCC + 0.5V DC Output Voltage DC Output Source or Sink Current DC VCC or Ground Current per Output Pin Storage Temperature Junction Temperature Rating to +7.0V +20mA to VCC + 0.5V +20mA to VCC + 0.5V ±50mA ±50mA to +150°C 140°C Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol VCC VI VO TA / Parameter Supply Voltage AC ACT Input Voltage Output Voltage Operating Temperature Minimum Input Edge Rate, AC Devices VIN from 30% to 70% of VCC, VCC 3.3V, 4.5V, 5.5V Minimum Input Edge Rate, ACT Devices VIN from 0.8V to 2.0V, VCC 4.5V, 5.5V Rating 2.0V to 6.0V 4.5V to 5.5V 0V to VCC 0V to VCC to +85°C 125mV/ns 125mV/ns

PDF Datasheet Preview

74AC273, 74ACT273 Octal D-Type Flip-Flop

January 2008
74AC273, 74ACT273 Octal D-Type Flip-Flop
• Ideal buffer for microprocessor or memory
• Eight edge-triggered D-type flip-flops
• Buffered common clock
• Buffered, asynchronous master reset
• See 377 for clock enable version
• See 373 for transparent latch version
• See 374 for 3-STATE version
• Outputs source/sink 24mA
• 74ACT273 has TTL-compatible inputs

The AC273 and ACT273 have eight edge-triggered D-type flip-flops with individual D-type inputs and Q outputs. The common buffered Clock CP and Master Reset MR input load and reset clear all flip-flops simultaneously.

The register is fully edge-triggered. The state of each D-type input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flipflop's Q output.

All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR input. The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements.
Ordering Information

Order Number

Package Number

Package Description
74AC273SC 74AC273SJ 74AC273MTC
74AC273PC 74ACT273SC 74ACT273SJ 74ACT273MTC

M20B M20D MTC20

N20A M20B M20D MTC20
20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide 20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.

All packages are lead free per JEDEC J-STD-020B standard.
74AC273, 74ACT273 Octal D-Type Flip-Flop

Connection Diagram

Logic Symbols

IEEE/IEC

Pin Description

Pin Names MR CP

Description Data Inputs Master Reset Clock Pulse Input Data Outputs

Logic Diagram

Mode Select-Function Table

Operating Mode Reset Clear Load ‘1' Load ‘0'

Inputs

MR CP Dn LXX

Outputs Qn L H L

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial
= LOW-to-HIGH Transition

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
1988 Fairchild Semiconductor Corporation
74AC273, 74ACT273 Octal D-Type Flip-Flop

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only.

Parameter

VCC IIK

VI IOK

VO IO ICC or IGND TSTG TJ

Supply Voltage DC Input Diode Current

VI = VI = VCC + DC Input Voltage DC Output Diode Current VO = VO = VCC + 0.5V DC Output Voltage DC Output Source or Sink Current DC VCC or Ground Current per Output Pin Storage Temperature Junction Temperature

Rating to +7.0V
+20mA to VCC + 0.5V
+20mA to VCC + 0.5V ±50mA ±50mA to +150°C 140°C

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings.

Symbol VCC

VI VO TA /

Parameter Supply Voltage

AC ACT Input Voltage Output Voltage Operating Temperature Minimum Input Edge Rate, AC Devices VIN from 30% to 70% of VCC, VCC 3.3V, 4.5V, 5.5V Minimum Input Edge Rate, ACT Devices VIN from 0.8V to 2.0V, VCC 4.5V, 5.5V

Rating
2.0V to 6.0V 4.5V to 5.5V
0V to VCC 0V to VCC to +85°C 125mV/ns
125mV/ns

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Datasheet ID: 74AC273SC 513093