74AC253SJ

74AC253SJ Datasheet

74AC253<br>• 74ACT253 Dual 4-Input Multiplexer with 3-STATE Outputs

Part	Datasheet
74AC253SJ	74AC253SJ (pdf)

Related Parts	Information
74AC253PC	74AC253PC
74AC253SJX	74AC253SJX
74AC253SC	74AC253SC
74AC253SCX	74AC253SCX

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74AC253 • 74ACT253 Dual 4-Input Multiplexer with 3-STATE Outputs 74AC253 • 74ACT253 Dual 4-Input Multiplexer with 3-STATE Outputs The AC/ACT253 is a dual 4-input multiplexer with 3-STATE outputs. It can select two bits of data from four sources using common select inputs. The outputs may be individually switched to a high impedance state with a HIGH on the respective Output Enable OE inputs, allowing the outputs to interface directly with bus oriented systems. s ICC and IOZ reduced by 50% s Multifunction capability s Non inverting 3-STATE outputs s Outputs source/sink 24 mA s ACT253 has TTL-compatible inputs Ordering Code: Order Number Package Number Package Description 74AC253SC M16A 16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow 74AC253SJ M16D 16-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 74AC253PC N16E 16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide 74ACT253SC M16A 16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow 74ACT253SJ M16D 16-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 74ACT253MTC MTC16 16-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide 74ACT253PC N16E 16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Device also available Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Diagrams Connection Diagram IEEE/IEC Pin Descriptions Pin Names S0, S1 OEa OEb Za, Zb Description Side A Data Inputs Side B Data Inputs Common Select Inputs Side A Output Enable Input Side B Output Enable Input 3-STATE Outputs is a trademark of Fairchild Semiconductor Corporation. 2000 Fairchild Semiconductor Corporation DS009946 74AC253 • 74ACT253 Functional Description The AC/ACT253 contains two identical 4-input multiplexers with 3-STATE outputs. They select two bits from four sources selected by common Select inputs S0, S1 . The 4-input multiplexers have individual Output Enable OEa, OEb inputs which, when HIGH, force the outputs to a high impedance High Z state. This device is the logic implementation of a 2-pole, 4-position switch, where the position of the switch is determined by the logic levels supplied to the two select inputs. The logic equations for the outputs are shown: Za = OEa • I0a • S1 • S0 + I1a • S1 • S0 + I2a • S1 • S0 + I3a • S1 • S0 Zb = OEb • I0b • S1 • S0 + I1b • S1 • S0 + I2b • S1 • S0 + I3b • S1 • S0 If the outputs of 3-STATE devices are tied together, all but one device must be in the high impedance state to avoid high currents that would exceed the maximum ratings. Designers should ensure that Output Enable signals to 3STATE devices whose outputs are tied together are designed so that there is no overlap. Truth Table Select Inputs Data Inputs Output Outputs Enable I0 I1 I2 I3 X XXXX H LXXX HXXX XLXX XHXX XX L X XXHX XXXL XXXH Address Inputs S0 and S1 are common to both sections. H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74AC253 • 74ACT253 Absolute Maximum Ratings Note 1 Supply Voltage VCC DC Input Diode Current IIK VI = −0.5V VI = VCC + 0.5V DC Input Voltage VI DC Output Diode Current IOK VO = −0.5V VO = VCC + 0.5V DC Output Voltage VO DC Output Source or Sink Current IO DC VCC or Ground Current per Output Pin ICC or IGND Storage Temperature TSTG Junction Temperature TJ

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74AC253
• 74ACT253 Dual 4-Input Multiplexer with 3-STATE Outputs
74AC253
• 74ACT253 Dual 4-Input Multiplexer with 3-STATE Outputs

The AC/ACT253 is a dual 4-input multiplexer with 3-STATE outputs. It can select two bits of data from four sources using common select inputs. The outputs may be individually switched to a high impedance state with a HIGH on the respective Output Enable OE inputs, allowing the outputs to interface directly with bus oriented systems.
s ICC and IOZ reduced by 50% s Multifunction capability s Non inverting 3-STATE outputs s Outputs source/sink 24 mA s ACT253 has TTL-compatible inputs
Ordering Code:

Order Number Package Number

Package Description
74AC253SC

M16A
16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow
74AC253SJ

M16D
16-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide
74AC253PC

N16E
16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
74ACT253SC

M16A
16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow
74ACT253SJ

M16D
16-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide
74ACT253MTC

MTC16
16-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide
74ACT253PC

N16E
16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Device also available Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Diagrams

Connection Diagram

IEEE/IEC

Pin Descriptions

Pin Names S0, S1 OEa OEb Za, Zb

Description Side A Data Inputs Side B Data Inputs Common Select Inputs Side A Output Enable Input Side B Output Enable Input 3-STATE Outputs
is a trademark of Fairchild Semiconductor Corporation.
2000 Fairchild Semiconductor Corporation DS009946
74AC253
• 74ACT253

Functional Description

The AC/ACT253 contains two identical 4-input multiplexers with 3-STATE outputs. They select two bits from four sources selected by common Select inputs S0, S1 . The 4-input multiplexers have individual Output Enable OEa, OEb inputs which, when HIGH, force the outputs to a high impedance High Z state. This device is the logic implementation of a 2-pole, 4-position switch, where the position of the switch is determined by the logic levels supplied to the two select inputs. The logic equations for the outputs are shown:

Za = OEa
• I0a
• S1
• S0 + I1a
• S1
• S0 +

I2a
• S1
• S0 + I3a
• S1
• S0

Zb = OEb
• I0b
• S1
• S0 + I1b
• S1
• S0 +

I2b
• S1
• S0 + I3b
• S1
• S0

If the outputs of 3-STATE devices are tied together, all but one device must be in the high impedance state to avoid high currents that would exceed the maximum ratings. Designers should ensure that Output Enable signals to 3STATE devices whose outputs are tied together are designed so that there is no overlap.

Truth Table

Select Inputs

Data Inputs

Output Outputs

Enable

I0 I1 I2 I3

X XXXX H

LXXX

HXXX

XLXX

XHXX

XX L X

XXHX

XXXL

XXXH

Address Inputs S0 and S1 are common to both sections. H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74AC253
• 74ACT253

Absolute Maximum Ratings Note 1

Supply Voltage VCC DC Input Diode Current IIK

VI = −0.5V VI = VCC + 0.5V DC Input Voltage VI DC Output Diode Current IOK VO = −0.5V VO = VCC + 0.5V DC Output Voltage VO DC Output Source
or Sink Current IO DC VCC or Ground Current
per Output Pin ICC or IGND Storage Temperature TSTG Junction Temperature TJ

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Datasheet ID: 74AC253SJ 513091