74AC175SJ

74AC175SJ Datasheet

74AC175, 74ACT175 Quad D-Type Flip-Flop

Part	Datasheet
74AC175SJ	74AC175SJ (pdf)

Related Parts	Information
74ACT175SJX	74ACT175SJX
74ACT175SJ	74ACT175SJ
74ACT175MTCX	74ACT175MTCX
74AC175PC	74AC175PC
74ACT175PC	74ACT175PC
74AC175MTCX	74AC175MTCX
74ACT175SCX	74ACT175SCX
74AC175SCX	74AC175SCX
74ACT175MTC	74ACT175MTC
74AC175SJX	74AC175SJX
74AC175MTC	74AC175MTC
74AC175SC	74AC175SC
74ACT175SC	74ACT175SC

PDF Datasheet Preview
74AC175, 74ACT175 Quad D-Type Flip-Flop 74AC175, 74ACT175 Quad D-Type Flip-Flop • ICC reduced by 50% • Edge-triggered D-type inputs • Buffered positive edge-triggered clock • Asynchronous common reset • True and complement output • Outputs source/sink 24mA • ACT175 has TTL-compatible inputs April 2007 The AC/ACT175 is a high-speed quad D-type flip-flop. The device is useful for general flip-flop requirements where clock and clear inputs are common. The information on the D-type inputs is stored during the LOW-toHIGH clock transition. Both true and complemented outputs of each flip-flop are provided. A Master Reset input resets all flip-flops, independent of the Clock or D-type inputs, when LOW. Ordering Information Order Number Package Number Package Description 74AC175SC 74AC175SJ 74AC175MTC 74AC175PC 74ACT175SC 74ACT175SJ 74ACT175MTC M16A M16D MTC16 N16E M16A M16D MTC16 16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow Body 16-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 16-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide 16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide 16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow Body 16-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 16-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. Connection Diagram Pin Descriptions Pin Names CP MR Description Data Inputs Clock Pulse Input Master Reset Input True Outputs Complement Outputs FACT is a trademark of Fairchild Semiconductor Corporation. 74AC175, 74ACT175 Quad D-Type Flip-Flop Logic Symbol IEEE/IEC Logic Diagram Functional Description The AC/ACT175 consists of four edge-triggered D-type flip-flops with individual D inputs and Q and Q outputs. The Clock and Master Reset are common. The four flipflops will store the state of their individual D inputs on the LOW-to-HIGH clock CP transition, causing individual Q and Q outputs to follow. A LOW input on the Master Reset MR will force all Q outputs LOW and Q outputs HIGH independent of Clock or Data inputs. The AC/ ACT175 is useful for general logic applications where a common Master Reset and Clock are acceptable. Truth Table Inputs tn, MR = H Dn L H Outputs tn+1 H = HIGH Voltage Level L = LOW Voltage Level tn = Bit Time before Clock Pulse tn+1 = Bit Time after Clock Pulse Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Figure 1988 Fairchild Semiconductor Corporation 74AC175, 74ACT175 Quad D-Type Flip-Flop Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Parameter VCC IIK VI IOK VO IO ICC or IGND TSTG TJ Supply Voltage DC Input Diode Current VI = VI = VCC + 0.5V DC Input Voltage DC Output Diode Current VO = VO = VCC + 0.5V DC Output Voltage DC Output Source or Sink Current DC VCC or Ground Current per Output Pin Storage Temperature Junction Temperature Rating to +7.0V +20mA to VCC + 0.5V +20mA to VCC + 0.5V ±50mA ±50mA to +150°C 140°C Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol VCC VI VO TA / Parameter Supply Voltage AC ACT Input Voltage Output Voltage Operating Temperature Minimum Input Edge Rate, AC Devices VIN from 30% to 70% of VCC, VCC 3.3V, 4.5V, 5.5V Minimum Input Edge Rate, ACT Devices VIN from 0.8V to 2.0V, VCC 4.5V, 5.5V Rating 2.0V to 6.0V 4.5V to 5.5V 0V to VCC 0V to VCC to +85°C 125mV/ns 125mV/ns

PDF Datasheet Preview

74AC175, 74ACT175 Quad D-Type Flip-Flop
74AC175, 74ACT175 Quad D-Type Flip-Flop
• ICC reduced by 50%
• Edge-triggered D-type inputs
• Buffered positive edge-triggered clock
• Asynchronous common reset
• True and complement output
• Outputs source/sink 24mA
• ACT175 has TTL-compatible inputs

April 2007

The AC/ACT175 is a high-speed quad D-type flip-flop. The device is useful for general flip-flop requirements where clock and clear inputs are common. The information on the D-type inputs is stored during the LOW-toHIGH clock transition. Both true and complemented outputs of each flip-flop are provided. A Master Reset input resets all flip-flops, independent of the Clock or D-type inputs, when LOW.
Ordering Information

Order Number

Package Number

Package Description
74AC175SC
74AC175SJ 74AC175MTC 74AC175PC 74ACT175SC
74ACT175SJ 74ACT175MTC

M16A

M16D MTC16 N16E M16A

M16D MTC16
16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow Body 16-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 16-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide 16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide 16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow Body 16-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 16-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.

Connection Diagram

Pin Descriptions

Pin Names CP MR

Description Data Inputs Clock Pulse Input Master Reset Input True Outputs Complement Outputs

FACT is a trademark of Fairchild Semiconductor Corporation.
74AC175, 74ACT175 Quad D-Type Flip-Flop

Logic Symbol

IEEE/IEC

Logic Diagram

Functional Description

The AC/ACT175 consists of four edge-triggered D-type flip-flops with individual D inputs and Q and Q outputs. The Clock and Master Reset are common. The four flipflops will store the state of their individual D inputs on the LOW-to-HIGH clock CP transition, causing individual Q and Q outputs to follow. A LOW input on the Master Reset MR will force all Q outputs LOW and Q outputs HIGH independent of Clock or Data inputs. The AC/ ACT175 is useful for general logic applications where a common Master Reset and Clock are acceptable.

Truth Table

Inputs tn, MR = H Dn L H

Outputs tn+1

H = HIGH Voltage Level L = LOW Voltage Level tn = Bit Time before Clock Pulse tn+1 = Bit Time after Clock Pulse

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

Figure
1988 Fairchild Semiconductor Corporation
74AC175, 74ACT175 Quad D-Type Flip-Flop

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only.

Parameter

VCC IIK

VI IOK

VO IO ICC or IGND TSTG TJ

Supply Voltage DC Input Diode Current

VI = VI = VCC + 0.5V DC Input Voltage DC Output Diode Current VO = VO = VCC + 0.5V DC Output Voltage DC Output Source or Sink Current DC VCC or Ground Current per Output Pin Storage Temperature Junction Temperature

Rating to +7.0V
+20mA to VCC + 0.5V
+20mA to VCC + 0.5V ±50mA ±50mA to +150°C 140°C

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings.

Symbol VCC

VI VO TA /

Parameter Supply Voltage

AC ACT Input Voltage Output Voltage Operating Temperature Minimum Input Edge Rate, AC Devices VIN from 30% to 70% of VCC, VCC 3.3V, 4.5V, 5.5V Minimum Input Edge Rate, ACT Devices VIN from 0.8V to 2.0V, VCC 4.5V, 5.5V

Rating
2.0V to 6.0V 4.5V to 5.5V
0V to VCC 0V to VCC to +85°C 125mV/ns
125mV/ns

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Datasheet ID: 74AC175SJ 513086