74AC174MTC

74AC174MTC Datasheet


74AC174<br>• 74ACT174 Hex D-Type Flip-Flop with Master Reset

Part Datasheet
74AC174MTC 74AC174MTC 74AC174MTC (pdf)
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74AC174
• 74ACT174 Hex D-Type Flip-Flop with Master Reset
74AC174
• 74ACT174 Hex D-Type Flip-Flop with Master Reset

The AC/ACT174 is a high-speed hex D-type flip-flop. The device is used primarily as a 6-bit edge-triggered storage register. The information on the D inputs is transferred to storage during the LOW-to-HIGH clock transition. The device has a Master Reset to simultaneously clear all flipflops.
s ICC reduced by 50% s Outputs source/sink 24 mA s ACT174 has TTL-compatible inputs
Ordering Code:

Order Number Package Number

Package Description
74AC174SC

M16A
16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow
74AC174SJ

M16D
16-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide
74AC174MTC

MTC16
16-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide
74AC174PC

N16E
16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
74ACT174SC

M16A
16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow
74ACT174SJ

M16D
16-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide
74ACT174MTC

MTC16
16-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide
74ACT174PC

N16E
16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbols

Connection Diagram

IEEE/IEC

Pin Descriptions

Pin Names CP MR

Description Data Inputs Clock Pulse Input Master Reset Input Outputs
is a trademark of Fairchild Semiconductor Corporation.
2000 Fairchild Semiconductor Corporation DS009935
74AC174
• 74ACT174

Functional Description

Truth Table

The AC/ACT174 consists of six edge-triggered D-type flipflops with individual D inputs and Q outputs. The Clock

Inputs

CP and Master Reset MR are common to all flip-flops. Each D input’s state is transferred to the corresponding flip-
flop’s output following the LOW-to-HIGH Clock CP transi-
tion. A LOW input to the Master Reset MR will force all outputs LOW independent of Clock or Data inputs. The AC/

ACT174 is useful for applications where the true output
only is required and the Clock and Master Reset are com-
mon to all storage elements.

H = HIGH Voltage Level
= LOW Voltage Level = LOW-to-HIGH Transition

X = Immaterial

Logic Diagram

Output Q L H L Q

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74AC174
• 74ACT174

Absolute Maximum Ratings Note 1

Supply Voltage VCC DC Input Diode Current IIK

VI = −0.5V VI = VCC + 0.5V DC Input Voltage VI DC Output Diode Current IOK VO = −0.5V V = VCC + 0.5V DC Output Voltage VO DC Output Source
or Sink Current IO DC VCC or Ground Current
per Output Pin ICC or IGND Storage Temperature TSTG Junction Temperature TJ

PDIP
−0.5V to +7.0V
−20 mA +20 mA −0.5V to VCC + 0.5V
−20 mA +20 mA −0.5V to V CC + 0.5V
±50 mA
±50 mA −65°C to +150°C
140°C

Recommended Operating Conditions

Supply Voltage VCC AC
More datasheets: S70GL02GP12FFI012 | S70GL02GP12FAIR20 | ELD-305SYGWA/S530-E2 | 74ACT174SJ | 74ACT174SJX | 74AC174SJX | 74AC174SJ | 74AC174MTCX | 74ACT174MTC | 74ACT174MTCX


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Datasheet ID: 74AC174MTC 513085