74ACT16244MTD

74ACT16244MTD Datasheet


74AC16244<br>• 74ACT16244 16-Bit Buffer/Line Driver with 3-STATE Outputs

Part Datasheet
74ACT16244MTD 74ACT16244MTD 74ACT16244MTD (pdf)
Related Parts Information
74ACT16244MTDX 74ACT16244MTDX 74ACT16244MTDX
74ACT16244SSCX 74ACT16244SSCX 74ACT16244SSCX
74ACT16244SSC 74ACT16244SSC 74ACT16244SSC
74AC16244SSCX 74AC16244SSCX 74AC16244SSCX
74AC16244SSC 74AC16244SSC 74AC16244SSC
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74AC16244
• 74ACT16244 16-Bit Buffer/Line Driver with 3-STATE Outputs
74AC16244
• 74ACT16244 16-Bit Buffer/Line Driver with 3-STATE Outputs

The AC16244 and ACT16244 contain sixteen non-inverting buffers with 3-STATE outputs designed to be employed as a memory and address driver, clock driver, or bus oriented transmitter/receiver. The device is nibble controlled. Each nibble has separate 3-STATE control inputs which can be shorted together for full 16-bit operation.
s Separate control logic for each byte and nibble s 16-bit version of the AC244/ACT244 s Outputs source/sink 24 mA s ACT16244 has TTL-compatible inputs
Ordering Code:

Order Number Package Number

Package Description
74AC16244SSC

MS48A
48-Lead Small Shrink Outline Package SSOP , JEDEC MO-118, Wide
74ACT16244SSC

MS48A
48-Lead Small Shrink Outline Package SSOP , JEDEC MO-118, Wide
74ACT16244MTD

MTD48
48-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbol

Connection Diagram

Pin Descriptions

Pin Names

OEn I0 - I15 O0 - 015

Output Enable Input Active LOW Inputs Outputs
is a trademark of Fairchild Semiconductor Corporation. 2005 Fairchild Semiconductor Corporation DS500295
74AC16244
• 74ACT16244

Functional Description

The AC16244 and ACT16244 contain sixteen non-inverting buffers with 3-STATE standard outputs. The device is nibble 4 bits controlled with each nibble functioning identically, but independent of the other. The control pins can be shorted together to obtain full 16-bit operation. The
3-STATE outputs are controlled by an Output Enable OEn input for each nibble. When OEn is LOW, the outputs are in 2-state mode. When OEn is HIGH, the outputs are in the high impedance mode, but this does not interfere with entering new data into the inputs.

Truth Tables

Inputs

Outputs

Inputs

Outputs

Inputs

L LOW Voltage Level H HIGH Voltage Level

Logic Diagram

Outputs

Inputs

X Immaterial Z High Impedance

Outputs
74AC16244
• 74ACT16244

Absolute Maximum Ratings Note 1

Supply Voltage VCC DC Input Diode Current IIK

VI 0.5V VI VCC 0.5V DC Output Diode Current IOK VO VCC 0.5V DC Output Voltage VO DC Output Source/Sink Current IO DC VCC or Ground Current per Output Pin

Junction Temperature

Storage Temperature
mA to VCC 0.5V r50 mA
r50 mA to

Recommended Operating Conditions

Supply Voltage VCC AC
2.0V to 6.0V
4.5V to 5.5V

Input Voltage VI Output Voltage VO Operating Temperature TA Minimum Input Edge Rate 'V/'t
0V to VCC 0V to VCC to

AC Devices

VIN from 30% to 70% VCC 3.3V, 4.5V, 5.5V Minimum Input Edge Rate 'V/'t
125 mV/ns
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Datasheet ID: 74ACT16244MTD 513081