74AC109SJ

74AC109SJ Datasheet

74AC109, 74ACT109 Dual JK Positive Edge-Triggered Flip-Flop

Part	Datasheet
74AC109SJ	74AC109SJ (pdf)

Related Parts	Information
74AC109SCX	74AC109SCX
74ACT109MTC	74ACT109MTC
74AC109MTCX	74AC109MTCX
74ACT109MTCX	74ACT109MTCX
74ACT109SCX	74ACT109SCX
74AC109MTC	74AC109MTC
74ACT109PC	74ACT109PC
74AC109SJX	74AC109SJX
74ACT109SC	74ACT109SC
74AC109PC	74AC109PC
74AC109SC	74AC109SC

PDF Datasheet Preview
74AC109, 74ACT109 Dual JK Positive Edge-Triggered Flip-Flop 74AC109, 74ACT109 Dual JK Positive Edge-Triggered Flip-Flop March 2007 • ICC reduced by 50% • Outputs source/sink 24mA • ACT109 has TTL-compatible inputs The AC/ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-Type flip-flop refer to AC/ACT74 data sheet by connecting the J and K inputs together. Asynchronous Inputs: LOW input to SD Set sets Q to HIGH level LOW input to CD Clear sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on CD and SD makes both Q and Q HIGH Ordering Information Order Number 74AC109SC 74AC109SJ 74AC109MTC 74ACT109SC 74AC109MTC 74ACT109PC Package Number M16A M16D MTC16 M16A MTC16 N16E Package Description 16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow 16-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 16-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide 16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow 16-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide 16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. Connection Diagram Pin Descriptions Pin Names J1, J2, K1, K2 CP1, CP2 CD1, CD2 SD1, SD2 Q1, Q2, Q1, Q2 Description Data Inputs Clock Pulse Inputs Direct Clear Inputs Direct Set Inputs Outputs FACT is a trademark of Fairchild Semiconductor Corporation. 74AC109, 74ACT109 Dual JK Positive Edge-Triggered Flip-Flop Logic Symbols IEEE/IEC Truth Table Each half. Inputs Outputs Toggle H = HIGH Voltage Level L = LOW Voltage Level = LOW-to-HIGH Transition X = Immaterial Q0 = Previous Q0 before LOW-to-HIGH Transition of Clock Logic Diagram One half shown. Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 1988 Fairchild Semiconductor Corporation 74AC109, 74ACT109 Dual JK Positive Edge-Triggered Flip-Flop Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Parameter VCC IIK VI IOK VO IO ICC or IGND TSTG TJ Supply Voltage DC Input Diode Current VI = VI = VCC + 0.5V DC Input Voltage DC Output Diode Current VO = VO = VCC + 0.5V DC Output Voltage DC Output Source or Sink Current DC VCC or Ground Current per Output Pin Storage Temperature Junction Temperature Rating to +7.0V +20mA to VCC + 0.5V +20mA to VCC + 0.5V ±50mA ±50mA to +150°C 140°C Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol VCC VI VO TA / Parameter Supply Voltage AC ACT Input Voltage Output Voltage Operating Temperature Minimum Input Edge Rate, AC Devices VIN from 30% to 70% of VCC, VCC 3.3V, 4.5V, 5.5V Minimum Input Edge Rate, ACT Devices VIN from 0.8V to 2.0V, VCC 4.5V, 5.5V

PDF Datasheet Preview

74AC109, 74ACT109 Dual JK Positive Edge-Triggered Flip-Flop
74AC109, 74ACT109 Dual JK Positive Edge-Triggered Flip-Flop

March 2007
• ICC reduced by 50%
• Outputs source/sink 24mA
• ACT109 has TTL-compatible inputs

The AC/ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-Type flip-flop refer to AC/ACT74 data sheet by connecting the J and K inputs together.

Asynchronous Inputs:

LOW input to SD Set sets Q to HIGH level LOW input to CD Clear sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on CD and SD makes both

Q and Q HIGH
Ordering Information

Order Number 74AC109SC 74AC109SJ 74AC109MTC
74ACT109SC 74AC109MTC
74ACT109PC

Package Number

M16A M16D MTC16

M16A MTC16

N16E

Package Description 16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow 16-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 16-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide 16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow 16-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide 16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.

Connection Diagram

Pin Descriptions

Pin Names

J1, J2, K1, K2 CP1, CP2 CD1, CD2 SD1, SD2 Q1, Q2, Q1, Q2

Description Data Inputs Clock Pulse Inputs Direct Clear Inputs Direct Set Inputs Outputs

FACT is a trademark of Fairchild Semiconductor Corporation.
74AC109, 74ACT109 Dual JK Positive Edge-Triggered Flip-Flop

Logic Symbols

IEEE/IEC

Truth Table

Each half.

Inputs

Outputs

Toggle

H = HIGH Voltage Level

L = LOW Voltage Level
= LOW-to-HIGH Transition

X = Immaterial Q0 = Previous Q0 before LOW-to-HIGH Transition of Clock

Logic Diagram

One half shown.

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
1988 Fairchild Semiconductor Corporation
74AC109, 74ACT109 Dual JK Positive Edge-Triggered Flip-Flop

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only.

Parameter

VCC IIK

VI IOK

VO IO ICC or IGND TSTG TJ

Supply Voltage DC Input Diode Current

VI = VI = VCC + 0.5V DC Input Voltage DC Output Diode Current VO = VO = VCC + 0.5V DC Output Voltage DC Output Source or Sink Current DC VCC or Ground Current per Output Pin Storage Temperature Junction Temperature

Rating to +7.0V
+20mA to VCC + 0.5V
+20mA to VCC + 0.5V ±50mA ±50mA to +150°C 140°C

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings.

Symbol VCC

VI VO TA /

Parameter Supply Voltage

AC ACT Input Voltage Output Voltage Operating Temperature Minimum Input Edge Rate, AC Devices VIN from 30% to 70% of VCC, VCC 3.3V, 4.5V, 5.5V Minimum Input Edge Rate, ACT Devices VIN from 0.8V to 2.0V, VCC 4.5V, 5.5V

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived 74AC109SJ Datasheet file may be downloaded here without warranties.

Datasheet ID: 74AC109SJ 513074