74ABT573CMTCX

74ABT573CMTCX Datasheet

74ABT573 Octal D-Type Latch with 3-STATE Outputs

Part	Datasheet
74ABT573CMTCX	74ABT573CMTCX (pdf)

Related Parts	Information
74ABT573CMSAX	74ABT573CMSAX
74ABT573CPC	74ABT573CPC
74ABT573CSCX	74ABT573CSCX
74ABT573CMTC	74ABT573CMTC
74ABT573CMSA	74ABT573CMSA
74ABT573CSC	74ABT573CSC
74ABT573CSJ	74ABT573CSJ
74ABT573CSJX	74ABT573CSJX

PDF Datasheet Preview
74ABT573 Octal D-Type Latch with 3-STATE Outputs December 2007 74ABT573 Octal D-Type Latch with 3-STATE Outputs • Inputs and outputs on opposite sides of package allow easy interface with microprocessors • Useful as input or output port for microprocessors • Functionally identical to ABT373 • 3-STATE outputs for bus interfacing • Output sink capability of 64mA, source capability of 32mA • Guaranteed output skew • Guaranteed multiple output switching specifications • Output switching specified for both 50pF and 250pF loads • Guaranteed simultaneous switching, noise level and dynamic threshold performance • Guaranteed latchup protection • High-impedance, glitch-free bus loading during entire power up and power down • Nondestructive, hot insertion capability The ABT573 is an octal latch with buffered common Latch Enable LE and buffered common Output Enable OE inputs. This device is functionally identical to the ABT373 but has broadside pinouts. Ordering Information Order Number 74ABT573CSC 74ABT573CSJ 74ABT573CMSA 74ABT573CMTC Package Number M20B M20D MSA20 MTC20 Package Description 20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 20-Lead Shrink Small Outline Package SSOP , JEDEC MO-150, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. All packages are lead free per JEDEC J-STD-020B standard. 74ABT573 Octal D-Type Latch with 3-STATE Outputs Connection Diagram Pin Descriptions Pin Names LE OE Descriptions Data Inputs Latch Enable Input Active HIGH 3-STATE Output Enable Input Active LOW 3-STATE Latch Outputs Logic Diagram Functional Description The ABT573 contains eight D-type latches with 3-STATE output buffers. When the Latch Enable LE input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The 3-STATE buffers are controlled by the Output Enable OE input. When OE is LOW, the buffers are in the bi-state mode. When OE is HIGH the buffers are in the high impedance mode but this does not interfere with entering new data into the latches. Function Table Inputs Outputs O H L O0 Z H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial O0 = Value stored from previous clock cycle Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 1993 Fairchild Semiconductor Corporation 74ABT573 Octal D-Type Latch with 3-STATE Outputs Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. TSTG TA TJ VCC VIN IIN VO Parameter Storage Temperature Ambient Temperature Under Bias Junction Temperature Under Bias VCC Pin Potential to Ground Pin Input Voltage 1 Input Current 1 Voltage Applied to Any Output Disabled or Power-Off State HIGH State Current Applied to Output in LOW State Max. DC Latchup Source Current Over Voltage Latchup I/O Rating to +150°C to +125°C to +150°C to +7.0V to +7.0V to +5.0mA to 5.5V to VCC twice the rated IOL mA Note Either voltage limit or current limit is sufficient to protect inputs. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. TA VCC / Parameter Free Air Ambient Temperature Supply Voltage Minimum Input Edge Rate Data Input Enable Input Rating to +85°C +4.5V to +5.5V 50mV/ns 20mV/ns 1993 Fairchild Semiconductor Corporation 74ABT573 Octal D-Type Latch with 3-STATE Outputs DC Electrical Characteristics Symbol VIH VIL VCD VOH VOL IIH IBVI IOZH IOZL IOS ICEX IZZ ICCH ICCL ICCZ ICCT

PDF Datasheet Preview

74ABT573 Octal D-Type Latch with 3-STATE Outputs

December 2007
74ABT573 Octal D-Type Latch with 3-STATE Outputs
• Inputs and outputs on opposite sides of package allow easy interface with microprocessors
• Useful as input or output port for microprocessors
• Functionally identical to ABT373
• 3-STATE outputs for bus interfacing
• Output sink capability of 64mA, source capability of
32mA
• Guaranteed output skew
• Guaranteed multiple output switching specifications
• Output switching specified for both 50pF and 250pF
loads
• Guaranteed simultaneous switching, noise level and
dynamic threshold performance
• Guaranteed latchup protection
• High-impedance, glitch-free bus loading during entire
power up and power down
• Nondestructive, hot insertion capability

The ABT573 is an octal latch with buffered common Latch Enable LE and buffered common Output Enable OE inputs.

This device is functionally identical to the ABT373 but has broadside pinouts.
Ordering Information

Order Number 74ABT573CSC
74ABT573CSJ 74ABT573CMSA
74ABT573CMTC

Package Number

M20B

M20D MSA20

MTC20

Package Description
20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide
20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide
20-Lead Shrink Small Outline Package SSOP , JEDEC MO-150, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.

All packages are lead free per JEDEC J-STD-020B standard.
74ABT573 Octal D-Type Latch with 3-STATE Outputs

Connection Diagram

Pin Descriptions

Pin Names LE OE

Descriptions Data Inputs Latch Enable Input Active HIGH 3-STATE Output Enable Input Active LOW 3-STATE Latch Outputs

Logic Diagram

Functional Description

The ABT573 contains eight D-type latches with 3-STATE output buffers. When the Latch Enable LE input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The 3-STATE buffers are controlled by the Output Enable OE input. When OE is LOW, the buffers are in the bi-state mode. When OE is HIGH the buffers are in the high impedance mode but this does not interfere with entering new data into the latches.

Function Table

Inputs

Outputs O H L O0 Z

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial O0 = Value stored from previous clock cycle

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
1993 Fairchild Semiconductor Corporation
74ABT573 Octal D-Type Latch with 3-STATE Outputs

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only.

TSTG TA TJ VCC VIN IIN VO

Parameter Storage Temperature Ambient Temperature Under Bias Junction Temperature Under Bias VCC Pin Potential to Ground Pin Input Voltage 1 Input Current 1 Voltage Applied to Any Output

Disabled or Power-Off State HIGH State Current Applied to Output in LOW State Max. DC Latchup Source Current Over Voltage Latchup I/O

Rating to +150°C to +125°C to +150°C
to +7.0V to +7.0V to +5.0mA
to 5.5V to VCC twice the rated IOL mA

Note Either voltage limit or current limit is sufficient to protect inputs.

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings.

TA VCC /

Parameter Free Air Ambient Temperature Supply Voltage Minimum Input Edge Rate

Data Input Enable Input

Rating to +85°C +4.5V to +5.5V
50mV/ns 20mV/ns
1993 Fairchild Semiconductor Corporation
74ABT573 Octal D-Type Latch with 3-STATE Outputs

DC Electrical Characteristics

Symbol VIH VIL VCD VOH

VOL IIH

IBVI

IOZH IOZL IOS ICEX IZZ ICCH ICCL ICCZ

ICCT

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Datasheet ID: 74ABT573CMTCX 513061