74ABT377CSC

74ABT377CSC Datasheet

74ABT377 Octal D-Type Flip-Flop with Clock Enable

Part	Datasheet
74ABT377CSC	74ABT377CSC (pdf)

Related Parts	Information
74ABT377CSJX	74ABT377CSJX
74ABT377CSJ	74ABT377CSJ
74ABT377CSCX	74ABT377CSCX
74ABT377CMSAX	74ABT377CMSAX
74ABT377CMSA	74ABT377CMSA
74ABT377CMTCX	74ABT377CMTCX

PDF Datasheet Preview
74ABT377 Octal D-Type Flip-Flop with Clock Enable 74ABT377 Octal D-Type Flip-Flop with Clock Enable The ABT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock CP input loads all flip-flops simultaneously when the Clock Enable CE is LOW. The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop’s Q output. The CE input must be stable only one setup time prior to the LOW-to-HIGH clock transition for predictable operation. s Clock enable for address and data synchronization applications s Eight edge-triggered D-type flip-flops s Buffered common clock s See ABT273 for master reset version s See ABT373 for transparent latch version s See ABT374 for 3-STATE version s Output sink capability of 64 mA, source capability of 32 mA s Guaranteed latchup protection s High impedance glitch free bus loading during entire power up and power down cycle s Non-destructive hot insertion capability s Disable time less than enable time to avoid bus contention Ordering Code: Order Number Package Number Package Description 74ABT377CSC M20B 20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide Body 74ABT377CSJ M20D 20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 74ABT377CMSA MSA20 20-Lead Shrink Small Outline Package SSOP , EIAJ TYPE II, 5.3mm Wide 74ABT377CMTC MTC20 20-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Names CE CP Truth Table Descriptions Data Inputs Clock Enable Active LOW Clock Pulse Input Data Outputs Operating Mode Inputs Output Load “1” Load “0” Hold CE I h Dn h I X Qn H L No Change Do Nothing X H X No Change H = HIGH Voltage Level X = Immaterial = LOW Voltage Level = LOW-to-HIGH Clock Transition h = HIGH Voltage Level one setup time prior to the LOW-to-HIGH Clock Transition I = LOW Voltage Level one setup time prior to the LOW-to-HIGH Clock Transition 1999 Fairchild Semiconductor Corporation DS011550 74ABT377 Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74ABT377 Absolute Maximum Ratings Note 1 Recommended Operating Storage Temperature −65°C to +150°C Conditions Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage Note 2 Input Current Note 2 Voltage Applied to Any Output −55°C to +125°C −55°C to +150°C −0.5V to +7.0V −0.5V to +7.0V −30 mA to mA Free Air Ambient Temperature Supply Voltage Minimum Input Edge Rate Data Input Enable Input −40°C to +85°C +4.5V to +5.5V 50 mV/ns 20 mV/ns in the Disabled or Power-OFF State −0.5V to +4.75V in the HIGH State Current Applied to Output −0.5V to VCC

PDF Datasheet Preview

74ABT377 Octal D-Type Flip-Flop with Clock Enable
74ABT377 Octal D-Type Flip-Flop with Clock Enable

The ABT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock CP input loads all flip-flops simultaneously when the Clock Enable CE is LOW.

The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop’s Q output. The CE input must be stable only one setup time prior to the LOW-to-HIGH clock transition for predictable operation.
s Clock enable for address and data synchronization applications
s Eight edge-triggered D-type flip-flops s Buffered common clock s See ABT273 for master reset version s See ABT373 for transparent latch version s See ABT374 for 3-STATE version s Output sink capability of 64 mA, source capability
of 32 mA s Guaranteed latchup protection s High impedance glitch free bus loading during entire
power up and power down cycle s Non-destructive hot insertion capability s Disable time less than enable time to avoid bus
contention
Ordering Code:

Order Number Package Number

Package Description
74ABT377CSC

M20B
20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide Body
74ABT377CSJ

M20D
20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide
74ABT377CMSA

MSA20
20-Lead Shrink Small Outline Package SSOP , EIAJ TYPE II, 5.3mm Wide
74ABT377CMTC

MTC20
20-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Pin Descriptions

Pin Names CE CP

Truth Table

Descriptions Data Inputs Clock Enable Active LOW Clock Pulse Input Data Outputs

Operating Mode

Inputs

Output

Load “1” Load “0” Hold

CE I h

Dn h I X

Qn H L No Change

Do Nothing X H X No Change

H = HIGH Voltage Level X = Immaterial
= LOW Voltage Level = LOW-to-HIGH Clock Transition
h = HIGH Voltage Level one setup time prior to the

LOW-to-HIGH Clock Transition

I = LOW Voltage Level one setup time prior to the

LOW-to-HIGH Clock Transition
1999 Fairchild Semiconductor Corporation DS011550
74ABT377

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74ABT377

Absolute Maximum Ratings Note 1

Recommended Operating

Storage Temperature
−65°C to +150°C Conditions

Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage Note 2 Input Current Note 2 Voltage Applied to Any Output
−55°C to +125°C −55°C to +150°C
−0.5V to +7.0V −0.5V to +7.0V −30 mA to mA

Free Air Ambient Temperature Supply Voltage Minimum Input Edge Rate

Data Input Enable Input
−40°C to +85°C +4.5V to +5.5V
50 mV/ns 20 mV/ns
in the Disabled or

Power-OFF State
−0.5V to +4.75V
in the HIGH State Current Applied to Output
−0.5V to VCC

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Datasheet ID: 74ABT377CSC 513057