74ABT374 Octal D-Type Flip-Flop with 3-STATE Outputs
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74ABT374CMTCX (pdf) |
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74ABT374CMSAX |
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74ABT374 Octal D-Type Flip-Flop with 3-STATE Outputs December 2007 74ABT374 Octal D-Type Flip-Flop with 3-STATE Outputs • Edge-triggered D-type inputs • Buffered positive edge-triggered clock • 3-STATE outputs for bus-oriented applications • Output sink capability of 64mA, source capability of 32mA • Guaranteed output skew • Guaranteed multiple output switching specifications • Output switching specified for both 50pF and 250pF loads • Guaranteed simultaneous switching, noise level and dynamic threshold performance • Guaranteed latchup protection • High-impedance, glitch-free bus loading during entire power up and power down cycle • Nondestructive, hot-insertion capability The ABT374 is an octal D-type flip-flop featuring separate D-type inputs for each flip-flop and 3-STATE outputs for bus-oriented applications. A buffered Clock CP and Output Enable OE are common to all flip-flops. Ordering Information Order Number 74ABT374CSC 74ABT374CSJ 74ABT374CMSA 74ABT374CMTC Package Number M20B M20D MSA20 MTC20 Package Description 20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 20-Lead Shrink Small Outline Package SSOP , JEDEC MO-150, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. All packages are lead free per JEDEC J-STD-020B standard. 74ABT374 Octal D-Type Flip-Flop with 3-STATE Outputs Connection Diagram Pin Descriptions Pin Names Data Inputs Clock Pulse Input Active Rising Edge 3-STATE Output Enable Input Active LOW 3-STATE Outputs Functional Description The ABT374 consists of eight edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock CP transition. With the Output Enable OE LOW, the contents of the eight flip-flops are available at the outputs. When OE is HIGH, the outputs are in a high impedance state. Operation of the OE input does not affect the state of the flip-flops. Logic Diagram Function Table Inputs OE CP D Internal Q NC L H L H NC Outputs Function Z Hold Z Hold Z Load Z Load L Data Available H Data Available NC No Change in Data NC No Change in Data H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance = LOW-to-HIGH Transition NC = No Change Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 1992 Fairchild Semiconductor Corporation 74ABT374 Octal D-Type Flip-Flop with 3-STATE Outputs Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. TSTG TA TJ VCC VIN IIN VO Parameter Storage Temperature Ambient Temperature Under Bias Junction Temperature Under Bias VCC Pin Potential to Ground Pin Input Voltage 1 Input Current 1 Voltage Applied to Any Output Disabled or Power-Off State HIGH State Current Applied to Output in LOW State Max. DC Latchup Source Current Across Common Operating Range OE Pin Other Pins Over Voltage Latchup I/O Rating to +150°C to +125°C to +150°C to +7.0V to +7.0V to +5.0mA to 5.5V to VCC twice the rated IOL mA Note Either voltage limit or current limit is sufficient to protect inputs. |
More datasheets: B88069X3751B502 | FAN5033MPX | NX5032SA-13.000000MHZ-G1 | 576 | 74ABT374CMSA | 74ABT374CSJX | 74ABT374CSC | 74ABT374CSCX | 74ABT374CMSAX | 74ABT374CSJ |
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