74ABT273CSC

74ABT273CSC Datasheet

74ABT273 Octal D-Type Flip-Flop

Part	Datasheet
74ABT273CSC	74ABT273CSC (pdf)

Related Parts	Information
74ABT273CMSAX	74ABT273CMSAX
74ABT273CSCX	74ABT273CSCX
74ABT273CSJX	74ABT273CSJX
74ABT273CSJ	74ABT273CSJ
74ABT273CMSA	74ABT273CMSA
74ABT273CMTC	74ABT273CMTC
74ABT273CMTCX	74ABT273CMTCX

PDF Datasheet Preview
74ABT273 Octal D-Type Flip-Flop 74ABT273 Octal D-Type Flip-Flop The ABT273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock CP and Master Reset MR inputs load and reset clear all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop’s Q output. All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR input. The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements. s Eight edge-triggered D-type flip-flops s Buffered common clock s Buffered, asynchronous Master Reset s See ABT377 for clock enable version s See ABT373 for transparent latch version s See ABT374 for 3-STATE version s Output sink capability of 64 mA, source capability of 32 mA s Guaranteed latchup protection s High impedance glitch free bus loading during entire power up and power down cycle s Non-destructive hot insertion capability s Disable time less than enable time to avoid bus conten- tion Ordering Code: Order Number Package Number Package Description 74ABT273CSC M20B 20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide Body 74ABT273CSJ M20D 20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 74ABT273CMSA MSA20 20-Lead Shrink Small Outline Package SSOP , EIAJ TYPE II, 5.3mm Wide 74ABT273CMTC MTC20 20-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Names MR CP Description Data Inputs Master Reset Active LOW Clock Pulse Input Active Rising Edge Data Outputs 1999 Fairchild Semiconductor Corporation DS011549 74ABT273 Truth Table Operating Mode Inputs MR CP Reset Clear Load “1” Load “0” H = HIGH Voltage Level steady state h = HIGH Voltage Level one setup time prior to the LOW-to-HIGH clock transition L = LOW Voltage Level steady state I = LOW Voltage Level one setup time prior to the LOW-to-HIGH clock transition = Immaterial = LOW-to-HIGH clock transition Logic Diagram Output Qn L H L Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74ABT273 Absolute Maximum Ratings Note 1 Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +150°C VCC Pin Potential to Ground Pin Input Voltage Note 2 −0.5V to +7.0V −0.5V to +7.0V Input Current Note 2 −30 mA to mA Voltage Applied to Any Output in the Disabled or Power-Off State −0.5V to +4.75V in the HIGH State Current Applied to Output −0.5V to VCC in LOW State Max DC Latchup Source Current twice the rated IOL mA −500 mA Across Comm Operating Range Over Voltage Latchup VCC + 4.5V Recommended Operating Conditions

PDF Datasheet Preview

74ABT273 Octal D-Type Flip-Flop
74ABT273 Octal D-Type Flip-Flop

The ABT273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock CP and Master Reset MR inputs load and reset clear all flip-flops simultaneously.

The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop’s Q output.

All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR input. The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements.
s Eight edge-triggered D-type flip-flops s Buffered common clock s Buffered, asynchronous Master Reset s See ABT377 for clock enable version s See ABT373 for transparent latch version s See ABT374 for 3-STATE version s Output sink capability of 64 mA, source capability of
32 mA s Guaranteed latchup protection s High impedance glitch free bus loading during entire
power up and power down cycle s Non-destructive hot insertion capability s Disable time less than enable time to avoid bus conten-
tion
Ordering Code:

Order Number Package Number

Package Description
74ABT273CSC

M20B
20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide Body
74ABT273CSJ

M20D
20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide
74ABT273CMSA

MSA20
20-Lead Shrink Small Outline Package SSOP , EIAJ TYPE II, 5.3mm Wide
74ABT273CMTC

MTC20
20-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Connection Diagram

Pin Descriptions

Pin Names MR CP

Description Data Inputs Master Reset Active LOW Clock Pulse Input Active Rising Edge Data Outputs
1999 Fairchild Semiconductor Corporation DS011549
74ABT273

Truth Table

Operating Mode

Inputs

MR CP

Reset Clear Load “1” Load “0”

H = HIGH Voltage Level steady state h = HIGH Voltage Level one setup time prior to the LOW-to-HIGH clock transition L = LOW Voltage Level steady state I = LOW Voltage Level one setup time prior to the LOW-to-HIGH clock transition
= Immaterial = LOW-to-HIGH clock transition

Logic Diagram

Output Qn L H L

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74ABT273

Absolute Maximum Ratings Note 1

Storage Temperature
−65°C to +150°C

Ambient Temperature under Bias
−55°C to +125°C

Junction Temperature under Bias
−55°C to +150°C

VCC Pin Potential to Ground Pin Input Voltage Note 2
−0.5V to +7.0V −0.5V to +7.0V

Input Current Note 2
−30 mA to mA

Voltage Applied to Any Output
in the Disabled or

Power-Off State
−0.5V to +4.75V
in the HIGH State Current Applied to Output
−0.5V to VCC
in LOW State Max DC Latchup Source Current
twice the rated IOL mA −500 mA

Across Comm Operating Range

Over Voltage Latchup

VCC + 4.5V

Recommended Operating Conditions

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Datasheet ID: 74ABT273CSC 513053