74ABT16652CSSCX

74ABT16652CSSCX Datasheet


74ABT16652 16-Bit Transceivers and Registers with 3-STATE Outputs

Part Datasheet
74ABT16652CSSCX 74ABT16652CSSCX 74ABT16652CSSCX (pdf)
Related Parts Information
74ABT16652CMTDX 74ABT16652CMTDX 74ABT16652CMTDX
74ABT16652CSSC 74ABT16652CSSC 74ABT16652CSSC
74ABT16652CMTD 74ABT16652CMTD 74ABT16652CMTD
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74ABT16652 16-Bit Transceivers and Registers with 3-STATE Outputs
74ABT16652 16-Bit Transceivers and Registers with 3-STATE Outputs

The ABT16652 consists of sixteen bus transceiver circuits with D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Each byte has separate control inputs which can be shorted together for full 16-bit operation. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes to HIGH logic level. Output Enable pins OEAB, OEBA are provided to control the transceiver function.
s Independent registers for A and B buses s Multiplexed real-time and stored data s Separate control logic for each byte s A and B output sink capability of 64 mA, source
capability of 32 mA s Guaranteed output skew s High impedance glitch free bus loading during entire
power up and power down cycle s Nondestructive hot insertion capability
Ordering Code:

Order Number Package Number

Package Description
74ABT16652CSSC

MS56A
56-Lead Shrink Small Outline Package SSOP , JEDEC MO-118, Wide
74ABT16652CMTD

MTD56
56-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Pin Descriptions

Connection Diagram

Pin Names

CPABn, CPBAn SABn, SBAn OEABn, OEBAn

Descriptions Data Register A Inputs/ 3-STATE Outputs Data Register B Inputs/ 3-STATE Outputs Clock Pulse Inputs Select Inputs Output Enable Inputs
1999 Fairchild Semiconductor Corporation DS011599.prf
74ABT16652

Functional Description

In the transceiver mode, data present at the HIGH impedance port may be stored in either the A or B register or both.

The select SABn, SBAn controls can multiplex stored and real-time.

The examples in Figure 1 demonstrate the four fundamental bus-management functions that can be performed with the ABT16652.

Data on the A or B data bus, or both can be stored in the internal D flip-flop by LOW to HIGH transitions at the appropriate Clock Inputs CPABn, CPBAn regardless of the Select or Output Enable Inputs. When SAB and SBA are in the real time transfer mode, it is also possible to store data without using the internal D flip-flops by simultaneously enabling OEABn and OEBAn. In this configuration each Output reinforces its Input. Thus when all other data sources to the two sets of bus lines are in a HIGH impedance state, each set of bus lines will remain at its last state.

Note A Real-Time Transfer Bus B to Bus A

Note C Storage

OEAB OEBA CPAB CPBA SAB SBA

Note B Real-Time Transfer Bus A to Bus B

OEAB OEBA CPAB CPBA SAB SBA

Note D Transfer Storage Data to A or B

OEAB OEBA CPAB CPBA SAB SBA

FIGURE

OEAB OEBA CPAB1 CPBA SAB SBA

L H or L H or L H
74ABT16652

Function Table

Inputs

Inputs/Outputs Note 1

Operating Mode

OEAB1 OEBA1 CPAB1 CPBA1 SAB1 SBA1 A0 thru A7 B0 thru B7

L X H L
or L or L
or L or L

X Input

Input

Isolation

Store A and B Data

X Input

Not Specified Store A, Hold B

X Input

Output

Store A in Both Registers
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Datasheet ID: 74ABT16652CSSCX 513042