74ABT16500CSSC

74ABT16500CSSC Datasheet

74ABT16500 18-Bit Universal Bus Transceivers with 3-STATE Outputs

Part	Datasheet
74ABT16500CSSC	74ABT16500CSSC (pdf)

Related Parts	Information
74ABT16500CMTDX	74ABT16500CMTDX
74ABT16500CSSCX	74ABT16500CSSCX
74ABT16500CMTD	74ABT16500CMTD

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74ABT16500 18-Bit Universal Bus Transceivers with 3-STATE Outputs 74ABT16500 18-Bit Universal Bus Transceivers with 3-STATE Outputs The ABT16500 18-bit universal bus transceiver combines D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes. Data flow in each direction is controlled by output-enable OEAB and OEBA , latch-enable LEAB and LEBA , and clock CLKAB and CLKBA inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CLKAB is held at a HIGH or LOW logic level. If LEAB is LOW, the A bus data is stored in the latch/flip-flop on the HIGH-to-LOW transition of CLKAB. Output-enable OEAB is active-high. When OEAB is HIGH, the outputs are active. When OEAB is LOW, the outputs are in the high-impedance state. Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, and CLKBA. The output enables are com- plementary OEAB is active HIGH and OEBA is active LOW . To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor the minimum value of the resistor is determined by the current-sourcing capability of the driver. s Combines D-Type latches and D-Type flip-flops for operation in transparent, latched, or clocked mode s Flow-through architecture optimizes PCB layout s Guaranteed latch-up protection s High impedance glitch free bus loading during entire power up and power down cycle s Non-destructive hot insertion capability Ordering Code: Order Number Package Number Package Description 74ABT16500CSSC MS56A 56-Lead Shrink Small Outline Package SSOP , JEDEC MO-118, Wide 74ABT16500CMTD MTD56 56-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending the letter suffix “X” to the ordering code. Connection Diagram Function Table Note 1 Pin Assignment for SSOP Inputs Output OEAB LEAB CLKAB A X B0 Note 2 X B0 Note 3 Note 1 A-to-B data flow is shown B-to-A flow is similar but uses OEBA, LEBA, and CLKBA. Note 2 Output level before the indicated steady-state input conditions were established. Note 3 Output level before the indicated steady-state input conditions were established, provided that CLKAB was LOW before LEAB went LOW. 1999 Fairchild Semiconductor Corporation DS011581.prf 74ABT16500 Logic Diagram 74ABT16500 Absolute Maximum Ratings Note 4 Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +150°C VCC Pin Potential to Ground Pin −0.5V to +7.0V Input Voltage Note 5 −0.5V to +7.0V Input Current Note 5 −30 mA to mA Voltage Applied to Any Output in the Disabled or Power-off State −0.5V to 5.5V in the HIGH State Current Applied to Output −0.5V to VCC in LOW State Max twice the rated IOL mA DC Latchup Source Current Over Voltage Latchup I/O −500 mA 10V Recommended Operating Conditions Free Air Ambient Temperature

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74ABT16500 18-Bit Universal Bus Transceivers with 3-STATE Outputs
74ABT16500 18-Bit Universal Bus Transceivers with 3-STATE Outputs

The ABT16500 18-bit universal bus transceiver combines D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes.

Data flow in each direction is controlled by output-enable OEAB and OEBA , latch-enable LEAB and LEBA , and clock CLKAB and CLKBA inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CLKAB is held at a HIGH or LOW logic level. If LEAB is LOW, the A bus data is stored in the latch/flip-flop on the HIGH-to-LOW transition of CLKAB. Output-enable OEAB is active-high. When OEAB is HIGH, the outputs are active. When OEAB is LOW, the outputs are in the high-impedance state.

Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, and CLKBA. The output enables are com-
plementary OEAB is active HIGH and OEBA is active LOW .

To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor the minimum value of the resistor is determined by the current-sourcing capability of the driver.
s Combines D-Type latches and D-Type flip-flops for operation in transparent, latched, or clocked mode
s Flow-through architecture optimizes PCB layout s Guaranteed latch-up protection s High impedance glitch free bus loading during entire
power up and power down cycle s Non-destructive hot insertion capability
Ordering Code:

Order Number Package Number

Package Description
74ABT16500CSSC

MS56A
56-Lead Shrink Small Outline Package SSOP , JEDEC MO-118, Wide
74ABT16500CMTD

MTD56
56-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the letter suffix “X” to the ordering code.

Connection Diagram

Function Table Note 1

Pin Assignment for SSOP

Inputs

Output

OEAB LEAB CLKAB A

X B0 Note 2

X B0 Note 3

Note 1 A-to-B data flow is shown B-to-A flow is similar but uses OEBA, LEBA, and CLKBA.

Note 2 Output level before the indicated steady-state input conditions were established.

Note 3 Output level before the indicated steady-state input conditions were established, provided that CLKAB was LOW before LEAB went LOW.
1999 Fairchild Semiconductor Corporation DS011581.prf
74ABT16500

Logic Diagram
74ABT16500

Absolute Maximum Ratings Note 4

Storage Temperature
−65°C to +150°C

Ambient Temperature under Bias
−55°C to +125°C

Junction Temperature under Bias
−55°C to +150°C

VCC Pin Potential to Ground Pin
−0.5V to +7.0V

Input Voltage Note 5
−0.5V to +7.0V

Input Current Note 5
−30 mA to mA

Voltage Applied to Any Output
in the Disabled or

Power-off State
−0.5V to 5.5V
in the HIGH State Current Applied to Output
−0.5V to VCC
in LOW State Max
twice the rated IOL mA

DC Latchup Source Current Over Voltage Latchup I/O
−500 mA 10V

Recommended Operating Conditions

Free Air Ambient Temperature

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Datasheet ID: 74ABT16500CSSC 513036