74ABT125CMTC

74ABT125CMTC Datasheet


74ABT125 Quad Buffer with 3-STATE Outputs

Part Datasheet
74ABT125CMTC 74ABT125CMTC 74ABT125CMTC (pdf)
Related Parts Information
74ABT125CSC 74ABT125CSC 74ABT125CSC
74ABT125CSJ 74ABT125CSJ 74ABT125CSJ
74ABT125CSJX 74ABT125CSJX 74ABT125CSJX
74ABT125CSCX 74ABT125CSCX 74ABT125CSCX
74ABT125CMTCX 74ABT125CMTCX 74ABT125CMTCX
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74ABT125 Quad Buffer with 3-STATE Outputs

January 2008
74ABT125 Quad Buffer with 3-STATE Outputs
• Non-inverting buffers
• Output sink capability of 64mA, source capability of
32mA
• Guaranteed latchup protection
• High impedance glitch free bus loading during entire
power up and power down cycle
• Nondestructive hot insertion capability
• Disable time less than enable time to avoid bus
contention

The ABT125 contains four independent non-inverting buffers with 3-STATE outputs.
Ordering Information

Order Number 74ABT125CSC
74ABT125CSJ 74ABT125CMTC

Package Number

M14A

M14D MTC14

Package Description
14-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow
14-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.

All packages are lead free per JEDEC J-STD-020B standard.

Connection Diagram

Pin Description

Pin Names An, Bn On

Description Inputs Outputs

Function Table

Inputs

Output On L H Z

H = HIGH Voltage Level L = LOW Voltage Level Z = HIGH Impedance X = Immaterial
74ABT125 Quad Buffer with 3-STATE Outputs

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only.

TSTG TA TJ VCC VIN IIN VO

Parameter Storage Temperature Ambient Temperature Under Bias Junction Temperature Under Bias VCC Pin Potential to Ground Pin Input Voltage 1 Input Current 1 Voltage Applied to Any Output

Disabled or Power-Off State HIGH State Current Applied to Output in LOW State Max. DC Latchup Source Current Across Comm Operating Range Over Voltage Latchup I/O

Rating to +150°C to +125°C to +150°C
to +7.0V to +7.0V to +5.0mA
to 5.5V to VCC twice the rated IOL mA

Note Either voltage limit or current limit is sufficient to protect inputs.

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings.

TA VCC /

Parameter Free Air Ambient Temperature Supply Voltage Minimum Input Edge Rate

Data Input Enable Input

Rating to +85°C +4.5V to +5.5V
50mV/ns 20mV/ns
1994 Fairchild Semiconductor Corporation
74ABT125 Quad Buffer with 3-STATE Outputs

DC Electrical Characteristics

Parameter

VIH Input HIGH Voltage VIL Input LOW Voltage VCD Input Clamp Diode Voltage VOH Output HIGH Voltage

VOL Output LOW Voltage IIH Input HIGH Current

IBVI Input HIGH Current Breakdown Test

IIL Input LOW Current

VID Input Leakage Test

Min. Min. Min. Max. Max.

Conditions

Recognized HIGH Signal

Recognized LOW Signal

IIN = IOH = IOH = IOL = 64mA VIN = 2.7V 2 VIN = VCC VIN = 7.0V
More datasheets: 1422600000 | 1420900000 | 1420700000 | 1421900000 | 1421700000 | 1421500000 | 74ABT125CSC | 74ABT125CSJ | 74ABT125CSJX | 74ABT125CSCX


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Datasheet ID: 74ABT125CMTC 513029