100336SCX

100336SCX Datasheet

100336 Low Power 4-Stage Counter/Shift Register

Part	Datasheet
100336SCX	100336SCX (pdf)

Related Parts	Information
100336QC	100336QC
100336QIX	100336QIX
100336QI	100336QI
100336QCX	100336QCX
100336SC	100336SC

PDF Datasheet Preview
100336 Low Power 4-Stage Counter/Shift Register 100336 Low Power 4-Stage Counter/Shift Register The 100336 operates as either a modulo-16 up/down counter or as a 4-bit bidirectional shift register. Three Select Sn inputs determine the mode of operation, as shown in the Function Select table. Two Count Enable CEP, CET inputs are provided for ease of cascading in multistage counters. One Count Enable CET input also doubles as a Serial Data D0 input for shift-up operation. For shift-down operation, D3 is the Serial Data input. In counting operations the Terminal Count TC output goes LOW when the counter reaches 15 in the count/up mode or 0 zero in the count/down mode. In the shift modes, the TC output repeats the Q3 output. The dual nature of this TC/Q3 output and the D0/CET input means that one interconnection from one stage to the next higher stage serves as the link for multistage counting or shift-up operation. The indi- vidual Preset Pn inputs are used to enter data in parallel or to preset the counter in programmable counter applications. A HIGH signal on the Master Reset MR input overrides all other inputs and asynchronously clears the flipflops. In addition, a synchronous clear is provided, as well as a complement function which synchronously inverts the contents of the flip-flops. All inputs have 50 pull-down resistors. s 40% power reduction of the 100136 s 2000V ESD protection s Pin/function compatible with 100136 s Voltage compensated operating range = −4.2V to −5.7V s Available to industrial grade temperature range Ordering Code: Order Number Package Number Package Description 100336SC M24B 24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 100336PC N24E 24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-010, Wide 100336QC V28A 28-Lead Plastic Lead Chip Carrier PLCC , JEDEC MO-047, Square 100336QI V28A 28-Lead Plastic Lead Chip Carrier PLCC , JEDEC MO-047, Square Industrial Temperature Range −40°C to +85°C Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagrams 24-Pin DIP/SOIC 28-Pin PLCC Logic Symbol 2000 Fairchild Semiconductor Corporation DS010584 100336 Function Select Table Function Parallel Load Complement Shift Left Shift Right Count Down Clear Count Up Hold Pin Descriptions Pin Names Clock Pulse Input Count Enable Parallel Input Active LOW D0/CET Serial Data Input/Count Enable Trickle Input Active LOW Select Inputs Master Reset Input D3 TC Preset Inputs Serial Data Input Terminal Count Output Data Outputs Complementary Data Outputs Truth Table Q0 = LSB Inputs Outputs MR S2 S1 S0 CEP D0/CET D3 CP Q3 Q2 Q1 Q0 Mode P3 P2 P1 P0 Preset Parallel Load L H X L H L X L H X L H L XX LX Q3 Q2 Q1 Q0 Invert D3 Q3 Q2 Q1 Shift to LSB

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100336 Low Power 4-Stage Counter/Shift Register
100336 Low Power 4-Stage Counter/Shift Register

The 100336 operates as either a modulo-16 up/down counter or as a 4-bit bidirectional shift register. Three Select Sn inputs determine the mode of operation, as shown in the Function Select table. Two Count Enable CEP, CET inputs are provided for ease of cascading in multistage counters. One Count Enable CET input also doubles as a Serial Data D0 input for shift-up operation. For shift-down operation, D3 is the Serial Data input. In counting operations the Terminal Count TC output goes LOW when the counter reaches 15 in the count/up mode or 0 zero in the count/down mode. In the shift modes, the TC output repeats the Q3 output. The dual nature of this TC/Q3 output and the D0/CET input means that one interconnection from one stage to the next higher stage serves as the link for multistage counting or shift-up operation. The indi-
vidual Preset Pn inputs are used to enter data in parallel or to preset the counter in programmable counter applications. A HIGH signal on the Master Reset MR input overrides all other inputs and asynchronously clears the flipflops. In addition, a synchronous clear is provided, as well as a complement function which synchronously inverts the contents of the flip-flops. All inputs have 50 pull-down resistors.
s 40% power reduction of the 100136 s 2000V ESD protection s Pin/function compatible with 100136 s Voltage compensated operating range = −4.2V to −5.7V s Available to industrial grade temperature range
Ordering Code:

Order Number Package Number

Package Description
100336SC

M24B
24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide
100336PC

N24E
24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-010, Wide
100336QC

V28A
28-Lead Plastic Lead Chip Carrier PLCC , JEDEC MO-047, Square
100336QI

V28A
28-Lead Plastic Lead Chip Carrier PLCC , JEDEC MO-047, Square Industrial Temperature Range −40°C to +85°C
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagrams
24-Pin DIP/SOIC
28-Pin PLCC

Logic Symbol
2000 Fairchild Semiconductor Corporation DS010584
100336

Function Select Table

Function

Parallel Load

Complement

Shift Left

Shift Right

Count Down

Clear

Count Up

Hold

Pin Descriptions

Pin Names

Clock Pulse Input

Count Enable Parallel Input Active LOW

D0/CET

Serial Data Input/Count Enable Trickle Input Active LOW

Select Inputs Master Reset Input

D3 TC

Preset Inputs Serial Data Input Terminal Count Output

Data Outputs Complementary Data Outputs

Truth Table

Q0 = LSB

Inputs

Outputs

MR S2 S1 S0 CEP D0/CET D3 CP Q3 Q2 Q1 Q0

Mode

P3 P2 P1 P0

Preset Parallel Load

L H X L H L X L H X L H L

XX LX

Q3 Q2 Q1 Q0

Invert

D3 Q3 Q2 Q1

Shift to LSB

More datasheets: DFMM-LCLC-1M | DFMM-LCLC-10M | DFMM-LCLC-5M | DFMM-LCLC-15M | DFMM-SCSC-1M | 100336QC | 100336QIX | 100336QI | 100336QCX | 100336SC

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Datasheet ID: 100336SCX 512969