100331QC

100331QC Datasheet

100331 Low Power Triple D-Type Flip-Flop

Part	Datasheet
100331QC	100331QC (pdf)

Related Parts	Information
100331QIX	100331QIX
100331SCX	100331SCX
100331QI	100331QI
100331QCX	100331QCX
100331SC	100331SC

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100331 Low Power Triple D-Type Flip-Flop 100331 Low Power Triple D-Type Flip-Flop The 100331 contains three D-type, edge-triggered master/ slave flip-flops with true and complement outputs, a Common Clock CPC , and Master Set MS and Master Reset MR inputs. Each flip-flop has individual Clock CPn , Direct Set SDn and Direct Clear CDn inputs. Data enters a master when both CPn and CPC are LOW and transfers to a slave when CPn or CPC or both go HIGH. The Master Set, Master Reset and individual CDn and SDn inputs override the Clock inputs. All inputs have 50 pull-down resistors. s 35% power reduction of the 100131 s 2000V ESD protection s Pin/function compatible with 100131 s Voltage compensated operating range = −4.2V to −5.7V s Available to industrial grade temperature range Ordering Code: Order Number Package Number Package Description 100331SC M24B 24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 100331PC N24E 24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-010, Wide 100331QC V28A 28-Lead Plastic Lead Chip Carrier PLCC , JEDEC MO-047, Square 100331QI V28A 28-Lead Plastic Lead Chip Carrier PLCC , JEDEC MO-047, Square Industrial Temperature Range −40°C to +85°C Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol Connection Diagrams 24-Pin DIP/SOIC Pin Descriptions Pin Names CPC SDn MR Q0-Q2 Description Individual Clock Inputs Common Clock Input Data Inputs Individual Direct Clear Inputs Individual Direct Set Inputs Master Reset Input Master Set Input Data Outputs Complementary Data Outputs 2000 Fairchild Semiconductor Corporation DS010262 28-Pin PLCC 100331 Truth Tables Synchronous Operation Each Flip-Flop Inputs L H L H SDn L CDn L H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care U = Undefined t = Time before CP Positive Transition + 1 = Time after CP Positive Transition = LOW-to-HIGH Transition Outputs Qn t + 1 L H L H Qn t Qn t Qn t Logic Diagram Asynchronous Operation Each Flip-Flop Inputs Outputs Qn t + 1 100331 Absolute Maximum Ratings Note 1 Storage Temperature TSTG Maximum Junction Temperature TJ Pin Potential to Ground Pin VEE Input Voltage DC Output Current DC Output HIGH ESD Note 2 −65°C to +150°C +150°C −7.0V to +0.5V VEE to +0.5V −50 mA 2000V Commercial Version Recommended Operating Conditions Case Temperature TC Commercial 0°C to +85°C Industrial −40°C to +85°C

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100331 Low Power Triple D-Type Flip-Flop
100331 Low Power Triple D-Type Flip-Flop

The 100331 contains three D-type, edge-triggered master/ slave flip-flops with true and complement outputs, a Common Clock CPC , and Master Set MS and Master Reset MR inputs. Each flip-flop has individual Clock CPn , Direct Set SDn and Direct Clear CDn inputs. Data enters a master when both CPn and CPC are LOW and transfers to a slave when CPn or CPC or both go HIGH. The Master Set, Master Reset and individual CDn and SDn inputs override the Clock inputs. All inputs have 50 pull-down resistors.
s 35% power reduction of the 100131 s 2000V ESD protection s Pin/function compatible with 100131 s Voltage compensated operating range = −4.2V to −5.7V s Available to industrial grade temperature range
Ordering Code:

Order Number Package Number

Package Description
100331SC

M24B
24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide
100331PC

N24E
24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-010, Wide
100331QC

V28A
28-Lead Plastic Lead Chip Carrier PLCC , JEDEC MO-047, Square
100331QI

V28A
28-Lead Plastic Lead Chip Carrier PLCC , JEDEC MO-047, Square Industrial Temperature Range −40°C to +85°C
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbol

Connection Diagrams
24-Pin DIP/SOIC

Pin Descriptions

Pin Names

CPC SDn MR

Q0-Q2

Description Individual Clock Inputs Common Clock Input Data Inputs Individual Direct Clear Inputs Individual Direct Set Inputs Master Reset Input Master Set Input Data Outputs Complementary Data Outputs
2000 Fairchild Semiconductor Corporation DS010262
28-Pin PLCC
100331

Truth Tables

Synchronous Operation Each Flip-Flop

Inputs

L H L H

SDn L

CDn L

H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care U = Undefined t = Time before CP Positive Transition
+ 1 = Time after CP Positive Transition = LOW-to-HIGH Transition

Outputs

Qn t + 1

L H L H Qn t Qn t Qn t

Logic Diagram

Asynchronous Operation Each Flip-Flop

Inputs

Outputs

Qn t + 1
100331

Absolute Maximum Ratings Note 1

Storage Temperature TSTG Maximum Junction Temperature TJ Pin Potential to Ground Pin VEE Input Voltage DC Output Current

DC Output HIGH ESD Note 2
−65°C to +150°C +150°C
−7.0V to +0.5V VEE to +0.5V
−50 mA 2000V

Commercial Version

Recommended Operating Conditions

Case Temperature TC Commercial
0°C to +85°C

Industrial
−40°C to +85°C

More datasheets: M9240123 YL001 | M9240123 YL002 | M9240123 YL005 | 3611 | 4112 | QTLP610CEBTR | 100331QIX | 100331SCX | 100331QI | 100331QCX

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Datasheet ID: 100331QC 512968