29F52SPC

29F52SPC Datasheet

29F52<br>• 29F53 8-Bit Registered Transceiver

Part	Datasheet
29F52SPC	29F52SPC (pdf)

Related Parts	Information
29F52SC	29F52SC

PDF Datasheet Preview
29F52 • 29F53 8-Bit Registered Transceiver 29F52 • 29F53 8-Bit Registered Transceiver The 29F52 and 29F53 are 8-bit registered transceivers. Two 8-bit back to back registers store data flowing in both directions between two bidirectional buses. Separate clock, clock enable and 3-STATE output enable signals are provided for each register. The output pins are guaranteed to sink 24 mA while the output pins are designed for 64 mA. The 29F53 is an inverting option of the 29F52. Both transceivers are AMD Am2952/2953 functional equivalents. s 8-bit registered transceivers s Separate clock, clock enable and 3-STATE output enable provided for each register s AMD Am2952/2953 functional equivalents s Both inverting and non-inverting options available s 24-Pin slimline package Ordering Code: Order Number Package Number Package Description 29F52SC M24B 24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 29F52SPC N24C 24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide 29F53SPC N24C 24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols 29F52 29F53 IEEE/IEC 29F52 IEEE/IEC 29F53 2000 Fairchild Semiconductor Corporation DS009606 29F52 • 29F53 Connection Diagrams Pin Assignment for DIP and SOIC 29F52 Pin Assignment for DIP 29F53 Unit Loading/Fan Out Pin Names OEA CPA CEA OEB CPB CEB A-Register Inputs/ B-Register 3-STATE Outputs B Register Inputs/ A-Register 3-STATE Outputs Output Enable A-Register A-Register Clock A-Register Clock Enable Output Enable B-Register B-Register Clock B-Register Clock Enable Output Control Internal Y-Output OE Q 29F52 29F53 Function Z Disable Outputs Enable Outputs H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = HIGH Impedance N = LOW-to-HIGH Transition NC = No Change U.L. HIGH/LOW 150/40 80 Input IIH/IIL Output IOH/IOL 70 µA/0.65 mA −3 mA/24 mA 20 mA 70 µA/0.65 mA −12 mA/64 mA 48 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA Register Function Table Applies to A or B Register Inputs Internal Function D CP CE NC Hold Data L Load Data 29F52 • 29F53 Block Diagrams 29F52 29F52 • 29F53 Block Diagrams Continued Block Diagrams continued 29F53 29F52 • 29F53 Absolute Maximum Ratings Note 1 Storage Temperature

PDF Datasheet Preview

29F52
• 29F53 8-Bit Registered Transceiver
29F52
• 29F53 8-Bit Registered Transceiver

The 29F52 and 29F53 are 8-bit registered transceivers. Two 8-bit back to back registers store data flowing in both directions between two bidirectional buses. Separate clock, clock enable and 3-STATE output enable signals are provided for each register. The output pins are guaranteed to sink 24 mA while the output pins are designed for 64 mA.

The 29F53 is an inverting option of the 29F52. Both transceivers are AMD Am2952/2953 functional equivalents.
s 8-bit registered transceivers s Separate clock, clock enable and 3-STATE output
enable provided for each register s AMD Am2952/2953 functional equivalents s Both inverting and non-inverting options available s 24-Pin slimline package
Ordering Code:

Order Number Package Number

Package Description
29F52SC

M24B
24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide
29F52SPC

N24C
24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
29F53SPC

N24C
24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbols
29F52
29F53

IEEE/IEC 29F52

IEEE/IEC 29F53
2000 Fairchild Semiconductor Corporation DS009606
29F52
• 29F53

Connection Diagrams

Pin Assignment for DIP and SOIC 29F52

Pin Assignment for DIP 29F53

Unit Loading/Fan Out

Pin Names

OEA CPA CEA OEB CPB CEB

A-Register Inputs/ B-Register 3-STATE Outputs B Register Inputs/ A-Register 3-STATE Outputs Output Enable A-Register A-Register Clock A-Register Clock Enable Output Enable B-Register B-Register Clock B-Register Clock Enable

Output Control

Internal Y-Output OE

Q 29F52 29F53

Function

Z Disable Outputs

Enable Outputs

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = HIGH Impedance N = LOW-to-HIGH Transition NC = No Change

U.L. HIGH/LOW 150/40 80

Input IIH/IIL Output IOH/IOL 70 µA/0.65 mA −3 mA/24 mA 20 mA 70 µA/0.65 mA −12 mA/64 mA 48 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA

Register Function Table Applies to A or B Register

Inputs

Internal

Function

D CP CE

NC Hold Data

L Load Data
29F52
• 29F53

Block Diagrams
29F52
29F52
• 29F53

Block Diagrams Continued

Block Diagrams continued
29F53
29F52
• 29F53

Absolute Maximum Ratings Note 1

Storage Temperature

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Datasheet ID: 29F52SPC 512657