P3041NXN7PNC
P3041NXN7PNC Datasheet
P3041 QorIQ Integrated Processor Hardware Specifications
| Part | Datasheet |
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P3041NXN7PNC |
P3041NXN7PNC (pdf) |
| Related Parts | Information |
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P3041NSN7NNC |
P3041NSN7NNC |
P3041NXE7PNC |
P3041NXE7PNC |
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| Freescale Semiconductor Data Sheet Technical Data P3041 QorIQ Integrated Processor Hardware Specifications P3041 mm x mm The P3041 QorIQ integrated processor utilizes four processor cores built on Power technology. The cores include high-performance data path acceleration logic and network and peripheral bus interfaces required for networking, telecom/datacom, wireless infrastructure, and aerospace applications. This chip can be used for combined control, data path, and application layer processing in routers, switches, base station controllers, and general-purpose embedded computing. Its high level of integration offers significant performance benefits compared to multiple discrete devices while also greatly simplifying board design. The chip includes the following functions and features: • Four e500mc Power Architecture cores, each with a backside 128 KB L2 cache with ECC Three levels of instructions User, supervisor, and hypervisor Independent boot and reset Secure boot capability • CoreNet fabric supporting coherent and non-coherent transactions amongst CoreNet end-points • CoreNet platform cache with ECC • CoreNet bridges between the CoreNet fabric the I/Os, datapath accelerators, and high and low speed peripheral interfaces • One 10-Gigabit Ethernet XAUI controller • Five 1-Gigabit Ethernet controllers SGMII interfaces Gbps SGMII interfaces RGMII interfaces • One 64-bit DDR3 SDRAM memory controller with ECC • Multicore programmable interrupt controller • Four I2C controllers • Four 2-pin UARTs or two 4-pin UARTs • Two 4-channel DMA engines • Enhanced local bus controller eLBC • Four PCI Express controllers/ports • Two serial controllers/ports sRIO port supporting version with features from • Two serial ATA SATA controllers • Enhanced secure digital host controller SD/MMC • Enhanced serial peripheral interfaces eSPI • 2x high-speed USB controllers with integrated PHYs Freescale Semiconductor, Inc. All rights reserved. Table of Contents 1 Pin Assignments and Reset States 1295 FC-PBGA Ball Layout Diagrams Pinout List 2 Electrical Characteristics Overall DC Electrical Characteristics Power-Up Sequencing Power-Down Requirements Power Characteristics Input Clocks RESET Initialization Power-On Ramp Rate DDR3 and DDR3L SDRAM Controller eSPI DUART Ethernet Datapath Three-Speed Ethernet dTSEC , Management Interface, IEEE Std USB. Enhanced Local Bus Interface eLBC Enhanced Secure Digital Host Controller eSDHC Multicore Programmable Interrupt Controller MPIC and Trust Specifications JTAG Controller. I2C 96 GPIO 99 High-Speed Serial Interfaces HSSI 100 3 Hardware Design Considerations 132 System Clocking 132 Supply Power Default Setting 139 Power Supply Design 141 Decoupling Recommendations 143 SerDes Block Power Supply Decoupling Freescale Semiconductor This figure shows the major functional units within the chip. Pin Assignments and Reset States eOpenPIC PreBoot Loader Security Monitor Internal BootROM Power Mgmt SD/MMC 2x DUART 4x I2C 2x USB PHY Clocks/Reset GPIO CCSR P3041 128-Kbyte Backside L2 Cache Power e500mc Core 32-Kbyte 32-Kbyte D-Cache I-Cache 1024-Kbyte Frontside CoreNet Platform Cache 64-bit DDR3/3L Memory Controller PAMU PAMU CoreNet Coherency Fabric PAMU Peripheral Access Mgmt Unit PAMU eLBC Security Queue Mgr RapidIO RMan Pattern Match Engine Buffer Mgr Frame Manager Parse, Classify, Distribute Buffer 10GE 2x DMA 18-Lane 5-GHz SerDes PCIe sRIO PCIe SATA Real Time Debug Watchpoint Cross Trigger Items on the same line have no ordering requirement with respect to one another. Items on separate lines must be ordered sequentially such that voltage rails on a previous step must reach 90% of their value before the voltage rails on the current step reach 10% of theirs. This figure provides the POVDD timing diagram. Fuse programming 1 POVDD VDD_CA_CB_PL 10% POVDD 10% POVDD 90% VDD_CA_VB_PL tPOVDD_VDD PORESET 90% OVDD tPOVDD_PROG tPOVDD_DELAY 90% OVDD tPOVDD_RST NOTE POVDD must be stable at V prior to initiating fuse programming. Figure POVDD Timing Diagram This table provides information on the power-down and power-up sequence parameters for POVDD. Table POVDD Timing 5 Driver Type Unit tPOVDD_DELAY SYSCLKs Notes 1 Freescale Semiconductor Electrical Characteristics Table POVDD Timing 5 Driver Type Unit Notes tPOVDD_PROG tPOVDD_VDD tPOVDD_RST Note: Delay required from the negation of PORESET to driving POVDD ramp up. Delay measured from PORESET negation at 90% OVDD to 10% POVDD ramp up. Delay required from fuse programming finished to POVDD ramp down start. Fuse programming must complete while POVDD is stable at V. No activity other than that required for secure boot fuse programming is permitted while POVDD driven to any voltage above GND, including the reading of the fuse block. The reading of the fuse block may only occur while POVDD = GND. After fuse programming is completed, it is required to return POVDD = GND. Delay required from POVDD ramp down complete to VDD_CA_CB_PL ramp down start. POVDD must be grounded to minimum 10% POVDD before VDD_CA_CB_PL is at 90% VDD. Delay required from POVDD ramp down complete to PORESET assertion. POVDD must be grounded to minimum 10% POVDD before PORESET assertion reaches 90% OVDD. Only two secure boot fuse programming events are permitted per lifetime of a device. To guarantee MCKE low during power up, the above sequencing for GVDD is required. If there is no concern about any of the DDR signals being in an indeterminate state during power up, the sequencing for GVDD is not required. WARNING Incorrect voltage select settings can lead to irreversible device damage. See Section “Supply Power Default Setting.” NOTE From a system standpoint, if any of the I/O power supplies ramp prior to the VDD_CA_CB_PL supplies, the I/Os associated with that I/O supply may drive a logic one or zero during power-up, and extra current may be drawn by the device. Power-Down Requirements 6 Ordering Information Please contact your local Freescale sales office or regional marketing team for ordering information. Part Numbering Nomenclature Table Part Numbering Nomenclature Generation Platform Number of Cores Derivative Qual Status Temperature Range Encryption Package Type P = 45 nm 01 = 1 core 02 = 2 core 04 = 4 core E = SEC Prototype Std temp present FC-PBGA 1200 MHz 1200 MT/s Rev N = SEC not Pb-free Industrial Extended present spheres 1333 MHz 1333 MT/s Rev qualification temp to 105 C FC-PBGA 1500 MHz C4 and sphere Pb-free Freescale Semiconductor Ordering Information Orderable Part Numbers Addressed by this Document This table provides the Freescale orderable part numbers addressed by this document for the chip. Table Orderable Part Numbers Addressed by This Document P3041NSE1MMB P P3041NSE7MMC P3041NSN1MMB P3041NSN7MMC P3041NSE1NNB P3041NSE7NNC P3041NSN1NNB P3041NSN7NNC P3041NSE1PNB P3041NSE7PNC P3041NSN1PNB P3041NSN7PNC P3041NXE1MMB P3041NXE7MMC P3041NXN1MMB P3041NXN7MMC P3041NXE1NNB P3041NXE7NNC P3041NXN1NNB P3041NXN7NNC P3041NXE1PNB P3041NXE7PNC P3041NXN1PNB P3041NXN7PNC 3 04 = 1 S = Std E = SEC 4 cores Industrial temp present FC-PBGA 1200 MHz 1200 MT/s C qualification Pb-free N = SEC not spheres present E = SEC present FC-PBGA N = C4 and 1333 MHz 1333 MT/s sphere N = SEC not Pb-free present E = SEC present P= 1500 MHz N = SEC not present X= Extended temp E = SEC present 1200 MHz 1200 MT/s N = SEC not present E = SEC present 1333 MHz 1333 MT/s N = SEC not present |
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