P2041NSN7PNC

P2041NSN7PNC Datasheet

P2040 QorIQ Integrated Processor Hardware Specifications

Part	Datasheet
P2041NSN7PNC	P2041NSN7PNC (pdf)

Related Parts	Information
P2040NSN7HLC	P2040NSN7HLC
P2040NSN7KLC	P2040NSN7KLC
P2041NSN7NNC	P2041NSN7NNC
P2041NSE7PNC	P2041NSE7PNC
P2041NXN7NNC	P2041NXN7NNC
P2041NSE7PNAC	P2041NSE7PNAC
P2041NXE7MMC	P2041NXE7MMC
P2041NSN7PNAC	P2041NSN7PNAC
P2041NXN7MMC	P2041NXN7MMC
P2040NSN7FLC	P2040NSN7FLC
P2040NXE7MMC	P2040NXE7MMC
P2041NSE7MMC	P2041NSE7MMC
P2041NSN7MMC	P2041NSN7MMC
P2041NSE7NNC	P2041NSE7NNC
P2041NXE7PNC	P2041NXE7PNC
P2041NXE7NNC	P2041NXE7NNC
P2040NSN1FLB	P2040NSN1FLB
P2040NSN1HLB	P2040NSN1HLB
P2040NSN1KLB	P2040NSN1KLB
P2040NSN1MMB	P2040NSN1MMB
P2040NXE1FLB	P2040NXE1FLB
P2040NXE1MMB	P2040NXE1MMB
P2041NSE1MMB	P2041NSE1MMB
P2041NSE1NNB	P2041NSE1NNB
P2041NSN1NNB	P2041NSN1NNB
P2041NXN1PNB	P2041NXN1PNB
P2041NXN1NNB	P2041NXN1NNB
P2041NXN1MMB	P2041NXN1MMB
P2041NXE1PNB	P2041NXE1PNB
P2041NXE1NNB	P2041NXE1NNB
P2041NXE1MMB	P2041NXE1MMB
P2041NSN1PNB	P2041NSN1PNB
P2041NSE1PNB	P2041NSE1PNB
P2040NSN7MMC	P2040NSN7MMC

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Freescale Semiconductor Data Sheet Technical Data P2040 QorIQ Integrated Processor Hardware Specifications P2040 23 mm x 23 mm The P2040 QorIQ integrated communication processor combines four Power processor cores with high performance data path acceleration logic and network and peripheral bus interfaces required for networking, telecom/datacom, wireless infrastructure, and aerospace applications. This chip can be used for combined control, data path, and application layer processing in routers, switches, base station controllers, and general-purpose embedded computing. Its high level of integration offers significant performance benefits compared to multiple discrete devices, while also greatly simplifying board design. This chip includes the following functions and features: • Four e500mc Power Architecture cores Three levels of instructions User, supervisor, and hypervisor Independent boot and reset Secure boot capability • CoreNet fabric supporting coherent and non-coherent transactions amongst CoreNet endpoints • One 1 MB CoreNet platform cache with ECC • CoreNet bridges between the CoreNet fabric the I/Os, data path accelerators, and high and low speed peripheral interfaces • Five 1-Gigabit Ethernet controllers Gbps SGMII interfaces RGMII interfaces • One 64-bit DDR3 and DDR3L SDRAM memory controller with ECC • Multicore programmable interrupt controller • Four I2C controllers • Four 2-pin UARTs or two 4-pin UARTs • Two 4-channel DMA engines • Enhanced local bus controller eLBC • Three PCI Express controllers/ports • Two serial controllers/ports sRIO port supporting version with features • Two serial ATA SATA controllers • Enhanced secure digital host controller SD/MMC • Enhanced serial peripheral interface eSPI • 2x high-speed USB controllers with integrated PHYs Freescale Semiconductor, Inc. All rights reserved. Table of Contents 1 Pin Assignments and Reset States 780 FC-PBGA Ball Layout Diagrams Pinout List 2 Electrical Characteristics Overall DC Electrical Characteristics Power Up Sequencing Power Down Requirements. Power Characteristics Thermal. Input Clocks RESET Initialization Power-on Ramp Rate DDR3 and DDR3L SDRAM Controller eSPI DUART Ethernet Data path Three-Speed Ethernet dTSEC , Management Interface, IEEE Std USB. Enhanced Local Bus Interface Enhanced Secure Digital Host Controller eSDHC Multicore Programmable Interrupt Controller MPIC Specifications JTAG Controller. I2C 79 GPIO 82 High-Speed Serial Interfaces HSSI 83 3 Hardware Design Considerations 110 System Clocking 110 Supply Power Default Setting 117 Power Supply Design 119 Decoupling Recommendations 121 SerDes Block Power Supply Decoupling Freescale Semiconductor This figure shows the major functional units within the chip. Pin Assignments and Reset States P2040 eOpenPIC PreBoot Loader Security Monitor Internal BootROM Power Mgmt SD/MMC 2x DUART 4x I2C 2x USB PHY Clocks/Reset GPIO CCSR PAMU eLBC Security Queue Mgr RapidIO RMan Pattern Match Engine Buffer Mgr Power e500mc Core 32-Kbyte 32-Kbyte D-Cache I-Cache 1024-Kbyte Frontside CoreNet Pleatform Cache 64-bit DDR3/3L Memory Controller PAMU CoreNet Coherency Fabric PAMU Peripheral Access Mgmt Unit Frame Manager Parse, Classify, Distribute Buffer 2x DMA 10-Lane 5-GHz SerDes Figure Block Diagram PCIe sRIO PCIe SATA Real Time Debug Watchpoint Cross Trigger Perf CoreNet Monitor Trace Only 100,000 POR cycles are permitted per lifetime of a device. All supplies must be at their stable values within 75 ms. Items on the same line have no ordering requirement with respect to one another. Items on separate lines must be ordered sequentially such that voltage rails on a previous step must reach 90% of their value before the voltage rails on the current step reach 10% of theirs. This figure provides the POVDD timing diagram. POVDD VDD_CA_CB_PL Fuse programming 1 10% POVDD 10% POVDD 90% VDD_CA_CB_PL tPOVDD_VDD PORESET 90% OVDD tPOVDD_PROG tPOVDD_DELAY 90% OVDD tPOVDD_RST NOTE POVDD must be stable at V prior to initiating fuse programming. Figure POVDD Timing Diagram This table provides information on the power-down and power-up sequence parameters for POVDD. Table POVDD Timing 5 Driver Type Unit Note tPOVDD_DELAY SYSCLKs tPOVDD_PROG tPOVDD_VDD tPOVDD_RST Note: Delay required from the negation of PORESET to driving POVDD ramp up. Delay measured from PORESET negation at 90% OVDD to 10% POVDD ramp up. Delay required from fuse programming finished to POVDD ramp down start. Fuse programming must complete while POVDD is stable at V. No activity other than that required for secure boot fuse programming is permitted while POVDD driven to any voltage above GND, including the reading of the fuse block. The reading of the fuse block may only occur while POVDD = GND. After fuse programming is completed, it is required to return POVDD = GND. Delay required from POVDD ramp down complete to VDD_CA_CB_PL ramp down start. POVDD must be grounded to minimum 10% POVDD before VDD_CA_CB_PL is at 90% VDD. Delay required from POVDD ramp down complete to PORESET assertion. POVDD must be grounded to minimum 10% POVDD before PORESET assertion reaches 90% OVDD. Only two secure boot fuse programming events are permitted per lifetime of a device. To guarantee MCKE low during power up, the above sequencing for GVDD is required. If there is no concern about any of the DDR signals being in an indeterminate state during power up, the sequencing for GVDD is not required. Freescale Semiconductor Electrical Characteristics WARNING Incorrect voltage select settings can lead to irreversible device damage. See Section “Supply Power Default Setting.” NOTE From a system standpoint, if any of the I/O power supplies ramp prior to the VDD_CA_CB_PL supplies, the I/Os associated with that I/O supply may drive a logic one or zero during power-up, and extra current may be drawn by the device. Power Down Requirements The power-down cycle must complete such that power supply values are below V before a new power-up cycle can be started. If performing secure boot fuse programming per Section “Power Up Sequencing,” it is required that POVDD = GND before the system is power cycled PORESET assertion or powered down VDD_CA_CB_PL ramp down per the required timing specified in Table VDD_CA_CB_PL and USB_VDD_1P0 must be ramped down simultaneously. USB_VDD_1P8_DECAP should starts ramping down only after USB_VDD_3P3 is below V. Power Characteristics This table shows the power dissipations of the VDD_CA_CB_PL supply for various operating platform clock frequencies versus the core and DDR clock frequencies. Table Device Power Dissipation 6 Ordering Information Contact your local Freescale sales office or regional marketing team for ordering information. Part Numbering Nomenclature Table Part Numbering Nomenclature Generation Platform Number of Cores Derivative Qual Status Temp. Range Encryption Package Type CPU Freq P = 45 nm 01 = 1 core E = SEC A = Rev 02 = 2 cores Prototype Std temp present FC-PBGA 667 MHz 1067 MT/s 04 = 4 cores N = SEC Pb-free M = B = Rev Industrial Extended not present spheres 800 MHz 1200 MT/s qualification temp to 105C FC-PBGA 1000 MHz C4 and sphere 1200 MHz Pb-free Orderable Part Numbers Addressed by this Document This table provides the Freescale orderable part numbers addressed by this document for the chip. Freescale Semiconductor Ordering Information Part Number p n nn n P2040NSE1FLB P P2040NSE7FLC P2040NSN1FLB P2040NSN7FLC P2040NSE1HLB P2040NSE7HLC P2040NSN1HLB P2040NSN7HLC P2040NSE1KLB P2040NSE7KLC P2040NSN1KLB P2040NSN7KLC P2040NSE1MMB P2040NSE7MMC P2040NSN1MMB P2040NSN7MMC P2040NXE1FLB P2040NXE7FLC P2040NXN1FLB P2040NXN7FLC P2040NXE1MMB P2040NXE7MMC P2040NXN1MMB P2040NXN7MMC 2 04 = 4 1 core N= Industrial qualification S = Std temp E = SEC present N = SEC not present E = SEC present N = SEC not present 1= FC-PBGA Pb-free spheres 7= FC-PBGA C4 and sphere Pb-free F= 667 MHz H= 800 MHz 1067 MT/s C E = SEC Present K= 1000 MHz N = SEC not present E = SEC Present 1200 MHz 1200 MT/s N = SEC not present X= Extended temp E = SEC Present 667 MHz 1067 MT/s N = SEC not present E = SEC Present 1200 MHz 1200 MT/s

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Freescale Semiconductor Data Sheet Technical Data

P2040 QorIQ Integrated Processor Hardware Specifications

P2040
23 mm x 23 mm

The P2040 QorIQ integrated communication processor combines four Power processor cores with high performance data path acceleration logic and network and peripheral bus interfaces required for networking, telecom/datacom, wireless infrastructure, and aerospace applications.

This chip can be used for combined control, data path, and application layer processing in routers, switches, base station controllers, and general-purpose embedded computing. Its high level of integration offers significant performance benefits compared to multiple discrete devices, while also greatly simplifying board design.

This chip includes the following functions and features:
• Four e500mc Power Architecture cores Three levels of instructions User, supervisor, and hypervisor Independent boot and reset Secure boot capability
• CoreNet fabric supporting coherent and non-coherent transactions amongst CoreNet endpoints
• One 1 MB CoreNet platform cache with ECC
• CoreNet bridges between the CoreNet fabric the I/Os, data
path accelerators, and high and low speed peripheral interfaces
• Five 1-Gigabit Ethernet controllers Gbps SGMII interfaces RGMII interfaces
• One 64-bit DDR3 and DDR3L SDRAM memory controller with ECC
• Multicore programmable interrupt controller
• Four I2C controllers
• Four 2-pin UARTs or two 4-pin UARTs
• Two 4-channel DMA engines
• Enhanced local bus controller eLBC
• Three PCI Express controllers/ports
• Two serial controllers/ports sRIO port supporting version with features
• Two serial ATA SATA controllers
• Enhanced secure digital host controller SD/MMC
• Enhanced serial peripheral interface eSPI
• 2x high-speed USB controllers with integrated PHYs

Freescale Semiconductor, Inc. All rights reserved.

Table of Contents
1 Pin Assignments and Reset States 780 FC-PBGA Ball Layout Diagrams Pinout List
2 Electrical Characteristics Overall DC Electrical Characteristics Power Up Sequencing Power Down Requirements. Power Characteristics Thermal. Input Clocks RESET Initialization Power-on Ramp Rate DDR3 and DDR3L SDRAM Controller eSPI DUART Ethernet Data path Three-Speed Ethernet dTSEC , Management Interface, IEEE Std USB. Enhanced Local Bus Interface Enhanced Secure Digital Host Controller eSDHC Multicore Programmable Interrupt Controller MPIC Specifications JTAG Controller.

I2C 79 GPIO 82 High-Speed Serial Interfaces HSSI 83 3 Hardware Design Considerations 110 System Clocking 110 Supply Power Default Setting 117 Power Supply Design 119 Decoupling Recommendations 121 SerDes Block Power Supply Decoupling
Freescale Semiconductor

This figure shows the major functional units within the chip.

Pin Assignments and Reset States

P2040
eOpenPIC PreBoot Loader Security Monitor Internal BootROM

Power Mgmt

SD/MMC
2x DUART 4x I2C 2x

USB PHY

Clocks/Reset

GPIO

CCSR

PAMU
eLBC

Security

Queue Mgr

RapidIO RMan

Pattern Match Engine

Buffer Mgr

Power e500mc Core
32-Kbyte 32-Kbyte D-Cache I-Cache
1024-Kbyte Frontside CoreNet Pleatform

Cache
64-bit DDR3/3L Memory Controller

PAMU

CoreNet Coherency Fabric

PAMU

Peripheral Access Mgmt Unit

Frame Manager

Parse, Classify, Distribute

Buffer
2x DMA
10-Lane 5-GHz SerDes

Figure Block Diagram

PCIe
sRIO

PCIe

SATA

Real Time Debug

Watchpoint Cross Trigger

Perf CoreNet Monitor Trace
Only 100,000 POR cycles are permitted per lifetime of a device. All supplies must be at their stable values within 75 ms. Items on the same line have no ordering requirement with respect to one another. Items on separate lines must be ordered sequentially such that voltage rails on a previous step must reach 90% of their value before the voltage rails on the current step reach 10% of theirs. This figure provides the POVDD timing diagram.

POVDD VDD_CA_CB_PL

Fuse programming 1 10% POVDD
10% POVDD
90% VDD_CA_CB_PL tPOVDD_VDD

PORESET
90% OVDD
tPOVDD_PROG tPOVDD_DELAY
90% OVDD
tPOVDD_RST

NOTE POVDD must be stable at V prior to initiating fuse programming.

Figure POVDD Timing Diagram

This table provides information on the power-down and power-up sequence parameters for POVDD. Table POVDD Timing 5

Driver Type

Unit

Note
tPOVDD_DELAY

SYSCLKs
tPOVDD_PROG
tPOVDD_VDD
tPOVDD_RST

Note:

Delay required from the negation of PORESET to driving POVDD ramp up. Delay measured from PORESET negation at 90% OVDD to 10% POVDD ramp up.

Delay required from fuse programming finished to POVDD ramp down start. Fuse programming must complete while POVDD is stable at V. No activity other than that required for secure boot fuse programming is permitted while POVDD driven to any voltage above GND, including the reading of the fuse block. The reading of the fuse block may only occur while POVDD = GND. After fuse programming is completed, it is required to return POVDD = GND.

Delay required from POVDD ramp down complete to VDD_CA_CB_PL ramp down start. POVDD must be grounded to minimum 10% POVDD before VDD_CA_CB_PL is at 90% VDD.

Delay required from POVDD ramp down complete to PORESET assertion. POVDD must be grounded to minimum 10% POVDD before PORESET assertion reaches 90% OVDD.

Only two secure boot fuse programming events are permitted per lifetime of a device.

To guarantee MCKE low during power up, the above sequencing for GVDD is required. If there is no concern about any of the DDR signals being in an indeterminate state during power up, the sequencing for GVDD is not required.

Freescale Semiconductor

Electrical Characteristics

WARNING

Incorrect voltage select settings can lead to irreversible device damage. See Section “Supply Power Default Setting.”

NOTE

From a system standpoint, if any of the I/O power supplies ramp prior to the VDD_CA_CB_PL supplies, the I/Os associated with that I/O supply may drive a logic one or zero during power-up, and extra current may be drawn by the device.

Power Down Requirements

The power-down cycle must complete such that power supply values are below V before a new power-up cycle can be started.

If performing secure boot fuse programming per Section “Power Up Sequencing,” it is required that POVDD = GND before the system is power cycled PORESET assertion or powered down VDD_CA_CB_PL ramp down per the required timing specified in Table

VDD_CA_CB_PL and USB_VDD_1P0 must be ramped down simultaneously. USB_VDD_1P8_DECAP should starts ramping down only after USB_VDD_3P3 is below V.

Power Characteristics

This table shows the power dissipations of the VDD_CA_CB_PL supply for various operating platform clock frequencies versus the core and DDR clock frequencies.

Table Device Power Dissipation
6 Ordering Information
Contact your local Freescale sales office or regional marketing team for ordering information.

Part Numbering Nomenclature

Table Part Numbering Nomenclature

Generation Platform

Number of Cores

Derivative

Qual Status

Temp. Range

Encryption

Package Type

CPU Freq

P = 45 nm 01 = 1 core

E = SEC

A = Rev
02 = 2 cores

Prototype Std temp present FC-PBGA 667 MHz 1067 MT/s
04 = 4 cores

N = SEC Pb-free

M = B = Rev

Industrial Extended not present spheres 800 MHz 1200 MT/s
qualification temp
to 105C

FC-PBGA 1000 MHz

C4 and
sphere 1200 MHz

Pb-free

Orderable Part Numbers Addressed by this Document

This table provides the Freescale orderable part numbers addressed by this document for the chip.

Freescale Semiconductor
Ordering Information

Part Number p n nn n

P2040NSE1FLB P P2040NSE7FLC

P2040NSN1FLB P2040NSN7FLC

P2040NSE1HLB P2040NSE7HLC

P2040NSN1HLB P2040NSN7HLC

P2040NSE1KLB P2040NSE7KLC

P2040NSN1KLB P2040NSN7KLC

P2040NSE1MMB P2040NSE7MMC

P2040NSN1MMB P2040NSN7MMC

P2040NXE1FLB P2040NXE7FLC

P2040NXN1FLB P2040NXN7FLC

P2040NXE1MMB P2040NXE7MMC

P2040NXN1MMB P2040NXN7MMC
2 04 = 4 1 core

N= Industrial qualification

S = Std temp

E = SEC present

N = SEC not present

E = SEC present

N = SEC not present
1= FC-PBGA

Pb-free spheres
7= FC-PBGA

C4 and sphere Pb-free

F= 667 MHz

H= 800 MHz
1067 MT/s C

E = SEC Present

K= 1000 MHz

N = SEC not present

E = SEC Present
1200 MHz 1200 MT/s

N = SEC not present

X= Extended
temp

E = SEC Present
667 MHz 1067 MT/s

N = SEC not present

E = SEC Present
1200 MHz 1200 MT/s

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived P2041NSN7PNC Datasheet file may be downloaded here without warranties.

Datasheet ID: P2041NSN7PNC 635621