MPC9772FAR2

MPC9772FAR2 Datasheet

Order number MPC9772 Rev 3, 05/2004

Part	Datasheet
MPC9772FAR2	MPC9772FAR2 (pdf)

Related Parts	Information
MPC9772AE	MPC9772AE
MPC9772FA	MPC9772FA

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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. MOTOROLA SEMICONDUCTOR TECHNICAL DATA 3.3V 1:12 LVCMOS PLL Clock Generator The MPC9772 is a 3.3V compatible, 1:12 PLL based clock generator targeted for high performance low-skew clock distribution in mid-range to high-performance networking, computing and telecom applications. With output frequencies up to 240 MHz and output skews less than 250 ps the device meets the needs of the most demanding clock applications. • 1:12 PLL based low-voltage clock generator • 3.3V power supply • Internal power-on reset • Generates clock signals up to 240 MHz • Maximum output skew of 250 ps • On-chip crystal oscillator clock reference • Two LVCMOS PLL reference clock inputs • External PLL feedback supports zero-delay capability • Various feedback and output dividers see application section • Supports up to three individual generated output clock frequencies • Synchronous output clock stop circuitry for each individual output for power down support • Drives up to 24 clock lines • Ambient temperature range to +85°C • Pin and function compatible to the MPC972 MPC9772 3.3V 1:12 LVCMOS PLL CLOCK GENERATOR FA SUFFIX 52 LEAD LQFP PACKAGE CASE 848D Functional Description The MPC9772 utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the MPC9772 requires the connection of the PLL feedback output QFB to feedback input FB_IN to close the PLL feedback path. The reference clock frequency and the divider for the feedback path determine the VCO frequency. Both must be selected to match the VCO frequency range. The MPC9772 features an extensive level of frequency programmability between the 12 outputs as well as the output to input relationships, for instance 1:1, 2:1, 3:1, 3:2, 4:1, 4:3, 5:1, 5:2, 5:3, 5:4, 5:6, 6:1, 8:1 and The QSYNC output will indicate when the coincident rising edges of the above relationships will occur. The selectability of the feedback frequency is independent of the output frequencies. This allows for very flexible programming of the input reference versus output frequency relationship. The output frequencies can be either odd or even multiples of the input reference. In addition the output frequency can be less than the input frequency for applications where a frequency needs to be reduced by a non-binary factor. The MPC9772 also supports the 180° phase shift of one of its output banks with respect to the other output banks. The QSYNC outputs reflects the phase relationship between the QA and QC outputs and can be used for the generation of system baseline timing signals. The REF_SEL pin selects the internal crystal oscillator or the LVCMOS compatible inputs as the reference clock signal. Two alternative LVCMOS compatible clock inputs are provided for clock redundancy support. The PLL_EN control selects the PLL bypass configuration for test and diagnosis. In this configuration, the selected input reference clock is routed directly to the output dividers bypassing the PLL. The PLL bypass is fully static and the minimum clock frequency specification and all other PLL characteristics do not apply. The outputs can be individually disabled stopped in logic low state by programming the serial CLOCK_STOP interface of the MPC9772. The MPC9772 has an internal power-on reset. The MPC9772 is fully 3.3V compatible and requires no external loop filter components. All inputs except XTAL accept LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 transmission lines. For series terminated transmission lines, each of the MPC9772 outputs can drive one or two traces giving the devices an effective fanout of The device is pin and function compatible to the MPC972 and is packaged in a 52-lead LQFP package. Motorola, Inc. 2004 For More Information On This Product, Go to: Freescale Semiconductor, Inc... MPC9772 Freescale Semiconductor, Inc. XTAL_IN XTAL_OUT CCLK0 CCLK1 CCLK_SEL REF_SEL FB_IN VCO_SEL PLL_EN FSEL_A[0:1] FSEL_B[0:1] FSEL_C[0:1] FSEL_FB[0:2] INV_CLK STOP_DATA STOP_CLK MR/OE All input resistors have a value of XTAL 0 VCC 1 0 1 0 ÷4, ÷6, ÷8, ÷12 ÷2 0 1 ÷4, ÷6, ÷8, ÷10 ÷2, ÷4, ÷6, ÷8 ÷4, ÷6, ÷8, ÷10 ÷12, ÷16, ÷20 SYNC PULSE POWER-ON RESET CLOCK STOP 12 Figure MPC9772 Logic Diagram

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Freescale Semiconductor, Inc...

Freescale Semiconductor, Inc.

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA
3.3V 1:12 LVCMOS PLL Clock Generator

The MPC9772 is a 3.3V compatible, 1:12 PLL based clock generator targeted for high performance low-skew clock distribution in mid-range to high-performance networking, computing and telecom applications. With output frequencies up to 240 MHz and output skews less than 250 ps the device meets the needs of the most demanding clock applications.
• 1:12 PLL based low-voltage clock generator
• 3.3V power supply
• Internal power-on reset
• Generates clock signals up to 240 MHz
• Maximum output skew of 250 ps
• On-chip crystal oscillator clock reference
• Two LVCMOS PLL reference clock inputs
• External PLL feedback supports zero-delay capability
• Various feedback and output dividers see application section
• Supports up to three individual generated output clock frequencies
• Synchronous output clock stop circuitry for each individual output for
power down support
• Drives up to 24 clock lines
• Ambient temperature range to +85°C
• Pin and function compatible to the MPC972

MPC9772
3.3V 1:12 LVCMOS PLL CLOCK GENERATOR

FA SUFFIX 52 LEAD LQFP PACKAGE

CASE 848D

Functional Description

The MPC9772 utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the MPC9772 requires the connection of the PLL feedback output QFB to feedback input FB_IN to close the PLL feedback path. The reference clock frequency and the divider for the feedback path determine the VCO frequency. Both must be selected to match the VCO frequency range. The MPC9772 features an extensive level of frequency programmability between the 12 outputs as well as the output to input relationships, for instance 1:1, 2:1, 3:1, 3:2, 4:1, 4:3, 5:1, 5:2, 5:3, 5:4, 5:6, 6:1, 8:1 and

The QSYNC output will indicate when the coincident rising edges of the above relationships will occur. The selectability of the feedback frequency is independent of the output frequencies. This allows for very flexible programming of the input reference versus output frequency relationship. The output frequencies can be either odd or even multiples of the input reference. In addition the output frequency can be less than the input frequency for applications where a frequency needs to be reduced by a non-binary factor. The MPC9772 also supports the 180° phase shift of one of its output banks with respect to the other output banks. The QSYNC outputs reflects the phase relationship between the QA and QC outputs and can be used for the generation of system baseline timing signals.

The REF_SEL pin selects the internal crystal oscillator or the LVCMOS compatible inputs as the reference clock signal. Two alternative LVCMOS compatible clock inputs are provided for clock redundancy support. The PLL_EN control selects the PLL bypass configuration for test and diagnosis. In this configuration, the selected input reference clock is routed directly to the output dividers bypassing the PLL. The PLL bypass is fully static and the minimum clock frequency specification and all other PLL characteristics do not apply.

The outputs can be individually disabled stopped in logic low state by programming the serial CLOCK_STOP interface of the MPC9772. The MPC9772 has an internal power-on reset.

The MPC9772 is fully 3.3V compatible and requires no external loop filter components. All inputs except XTAL accept LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 transmission lines. For series terminated transmission lines, each of the MPC9772 outputs can drive one or two traces giving the devices an effective fanout of The device is pin and function compatible to the MPC972 and is packaged in a 52-lead LQFP package.

Motorola, Inc. 2004

For More Information On This Product, Go to:

Freescale Semiconductor, Inc...

MPC9772

Freescale Semiconductor, Inc.

XTAL_IN XTAL_OUT

CCLK0 CCLK1 CCLK_SEL

REF_SEL FB_IN

VCO_SEL PLL_EN

FSEL_A[0:1] FSEL_B[0:1] FSEL_C[0:1] FSEL_FB[0:2]

INV_CLK

STOP_DATA STOP_CLK MR/OE

All input resistors have a value of

XTAL 0 VCC 1 0 1
0 ÷4, ÷6, ÷8, ÷12
÷2 0
1 ÷4, ÷6, ÷8, ÷10
÷2, ÷4, ÷6, ÷8
÷4, ÷6, ÷8, ÷10 ÷12, ÷16, ÷20

SYNC PULSE

POWER-ON RESET

CLOCK STOP 12

Figure MPC9772 Logic Diagram

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Datasheet ID: MPC9772FAR2 635589