MPC962305D-1H

MPC962305D-1H Datasheet

Order number MPC962305 Rev 5, 08/2004

Part	Datasheet
MPC962305D-1H	MPC962305D-1H (pdf)

Related Parts	Information
MPC962309D-1	MPC962309D-1
MPC962309D-1H	MPC962309D-1H
MPC962309DT-1H	MPC962309DT-1H
MPC962305DT-1H	MPC962305DT-1H
MPC962305D-1	MPC962305D-1

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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. MOTOROLA SEMICONDUCTOR TECHNICAL DATA Low-Cost V Zero Delay Buffer The MPC962309 is a zero delay buffer designed to distribute high-speed clocks. Available in a 16-pin SOIC or TSSOP package, the device accepts one reference input and drives nine low-skew clocks. The MPC962305 is the 8-pin version of the MPC962309 which drives five outputs with one reference input. The -1H versions of these devices have higher drive than the -1 devices and can operate up to 100/-133 MHz frequencies. These parts have on-chip PLLs which lock to an input clock presented on the REF pin. The PLL feedback is on-chip and is obtained from the CLOCKOUT pad. MPC962305 MPC962309 D SUFFIX 8-LEAD SOIC PACKAGE CASE 751-06 • 1:5 LVCMOS zero-delay buffer MPC962305 • 1:9 LVCMOS zero-delay buffer MPC962309 • Zero input-output propagation delay • Multiple low-skew outputs • 250 ps max output-output skew • 700 ps max device-device skew • Supports a clock I/O frequency range of 10 MHz to 133 MHz, compatible with CPU and PCI bus frequencies • Low jitter, 200 ps max cycle-cycle, and compatible with based systems • Test Mode to bypass PLL MPC962309 only. See “Select Input Decoding” • 8-pin SOIC or 8-pin TSSOP package MPC962305 ;16-pin SOIC or 16-pin TSSOP package MPC962309 • Single V supply • Ambient temperature range to +85°C • Compatible with the CY2305, CY23S05, CY2309, CY23S09 • Spread spectrum compatible Functional Description DT SUFFIX 8-LEAD TSSOP PACKAGE CASE 948J-01 D SUFFIX 16-LEAD SOIC PACKAGE CASE 751B-05 DT SUFFIX 16-LEAD TSSOP PACKAGE CASE 948F-01 The MPC962309 has two banks of four outputs each, which can be controlled by the Select Inputs as shown in Table 3.Select Input Decoding for MPC962309. Bank B can be tri-stated if all of the outputs are not required. Select inputs also allow the input clock to be directly applied to the outputs for chip and system testing purposes. The MPC962305 and MPC962309 PLLs enters a power down state when there are no rising edges on the REF input. During this state, all of the outputs are in tristate, the PLL is turned off, and there is less than µA of current draw for the device. The PLL shuts down in one additional case as shown in Table 3.Select Input Decoding for MPC962309. Multiple MPC962305 and MPC962309 devices can accept the same input clock and distribute it throughout the system. In this situation, the difference between the output skews of two devices will be less than 700 ps. All outputs have less than 200 ps of cycle-cycle jitter. The input-to-output propagation delay on both devices is guaranteed to be less than 350 ps and the output-to-output skew is guaranteed to be less than 250 ps. The MPC962305 and MPC962309 are available in two/three different configurations, as shown on the ordering information page. The MPC962305-1/MPC962309-1 are the base parts. High drive versions of those devices, MPC962305-1H and MPC962309-1H, are available to provide faster rise and fall times of the base device. Motorola, Inc. 2004 For More Information On This Product, Go to: Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. MPC962305 MPC962309 Block Diagram PLL MUX Select Input Decoding CLKOUT CLKA1 CLKA2 CLKA3 CLKA4 CLKB1 CLKB2 CLKB3 CLKB4 Pin Configuration SOIC/TSSOP Top View REF 1 CLKA1 2 CLKA2 3 VDD 4 GND 5 CLKB1 6 CLKB2 7 16 CLKOUT 15 CLKA4 14 CLKA3 13 VDD 12 GND 11 CLKB4 10 CLKB3 9 S1 CLK2 CLK1 GND SOIC/TSSOP Top View CLKOUT CLK4 VDD CLK3 Table Pin Description for MPC962309 Signal REF1 Input reference frequency, 5 V-tolerant input CLKA12 Buffered clock output, Bank A CLKA22 Buffered clock output, Bank A V supply Ground CLKB12 Buffered clock output, Bank B CLKB22 Buffered clock output, Bank B Select input, bit 2 Select input, bit 1 CLKB32 Table Ordering Information MPC962305D-1 MPC962305D-1R2 MPC962305D-1H MPC962305D-1HR2 MPC962305DT-1H MPC962305DT-1HR2 MPC962309D-1 MPC962309D-1R2 MPC962309D-1H MPC962309D-1HR2 MPC962309DT-1H MPC962309DT-1HR2 Ordering Code Package Type 8-pin 150-mil SOIC 8-pin 150-mil SOIC-Tape and Reel 8-pin 150-mil SOIC 8-pin 150-mil SOIC-Tape and Reel 8-pin 150-mil TSSOP 8-pin 150-mil TSSOP-Tape and Reel 16-pin 150-mil SOIC 16-pin 150-mil SOIC-Tape and Reel 16-pin 150-mil SOIC 16-pin 150-mil SOIC-Tape and Reel 16-pin 4.4-mm TSSOP 16-pin 4.4-mm TSSOP-Tape and Reel Freescale Semiconductor, Inc... TIMING SOLUTIONS For More Informat6ion On This Product, Go to: MOTOROLA Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. MPC962305 MPC962309 PACKAGE DIMENSIONS D SUFFIX 8-LEAD SOIC PACKAGE CASE 751-06 ISSUE T SEATING PLANE M C B S A S NOTES DIMENSIONING AND TOLERANCING PER ASME Y14.5M, DIMENSIONS ARE IN MILLIMETER. DIMENSION D AND E DO NOT INCLUDE MOLD PROTRUSION. MAXIMUM MOLD PROTRUSION PER SIDE. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS DIM MIN MAX D SUFFIX STYLE 1 PIN EMITTER COLLECTOR STYLE 2 PIN COLLECTOR, DIE, #1 COLLECTOR, #1 STYLE 4 PIN ANODE COLLECTOR EMITTER COLLECTOR, #2 COLLECTOR, #2 IS3. SDURAEIN,K#2 DRAIN, #2 ANODE EMITTER BASE EMITTER PIN'S NUMBER BASE, #2 EMITTER, #2 BASE, #1 EMITTAER, #1 GATE, #2 SOURCE, #2 GATE, #1 SO0U.2RC5E, #1 ANODE COMMON CATHODE STYLE 5 PIN DRAI1N STY1PL6IEN SOURCE STYLE 7 PIN INPUT M STTYPLAIEN 81B:. COLLECTOR, DIE #1

PDF Datasheet Preview

Freescale Semiconductor, Inc...

Freescale Semiconductor, Inc.

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Low-Cost V Zero Delay Buffer

The MPC962309 is a zero delay buffer designed to distribute high-speed clocks. Available in a 16-pin SOIC or TSSOP package, the device accepts one reference input and drives nine low-skew clocks. The MPC962305 is the 8-pin version of the MPC962309 which drives five outputs with one reference input. The -1H versions of these devices have higher drive than the -1 devices and can operate up to 100/-133 MHz frequencies. These parts have on-chip PLLs which lock to an input clock presented on the REF pin. The PLL feedback is on-chip and is obtained from the CLOCKOUT pad.

MPC962305 MPC962309

D SUFFIX 8-LEAD SOIC PACKAGE

CASE 751-06
• 1:5 LVCMOS zero-delay buffer MPC962305
• 1:9 LVCMOS zero-delay buffer MPC962309
• Zero input-output propagation delay
• Multiple low-skew outputs
• 250 ps max output-output skew
• 700 ps max device-device skew
• Supports a clock I/O frequency range of 10 MHz to 133 MHz,
compatible with CPU and PCI bus frequencies
• Low jitter, 200 ps max cycle-cycle, and compatible with based
systems
• Test Mode to bypass PLL MPC962309 only. See “Select Input Decoding”
• 8-pin SOIC or 8-pin TSSOP package MPC962305 ;16-pin SOIC or 16-pin

TSSOP package MPC962309
• Single V supply
• Ambient temperature range to +85°C
• Compatible with the CY2305, CY23S05, CY2309, CY23S09
• Spread spectrum compatible

Functional Description

DT SUFFIX 8-LEAD TSSOP PACKAGE

CASE 948J-01

D SUFFIX 16-LEAD SOIC PACKAGE

CASE 751B-05

DT SUFFIX 16-LEAD TSSOP PACKAGE

CASE 948F-01

The MPC962309 has two banks of four outputs each, which can be controlled by the Select Inputs as shown in Table 3.Select Input Decoding for MPC962309. Bank B can be tri-stated if all of the outputs are not required. Select inputs also allow the input clock to be directly applied to the outputs for chip and system testing purposes.

The MPC962305 and MPC962309 PLLs enters a power down state when there are no rising edges on the REF input. During this state, all of the outputs are in tristate, the PLL is turned off, and there is less than µA of current draw for the device. The PLL shuts down in one additional case as shown in Table 3.Select Input Decoding for MPC962309.

Multiple MPC962305 and MPC962309 devices can accept the same input clock and distribute it throughout the system. In this situation, the difference between the output skews of two devices will be less than 700 ps.

All outputs have less than 200 ps of cycle-cycle jitter. The input-to-output propagation delay on both devices is guaranteed to be less than 350 ps and the output-to-output skew is guaranteed to be less than 250 ps.
The MPC962305 and MPC962309 are available in two/three different configurations, as shown on the ordering information page. The MPC962305-1/MPC962309-1 are the base parts. High drive versions of those devices, MPC962305-1H and MPC962309-1H, are available to provide faster rise and fall times of the base device.

Motorola, Inc. 2004

For More Information On This Product, Go to:

Freescale Semiconductor, Inc...

Freescale Semiconductor, Inc.

MPC962305 MPC962309

Block Diagram

PLL MUX

Select Input

Decoding

CLKOUT CLKA1 CLKA2 CLKA3 CLKA4

CLKB1 CLKB2 CLKB3 CLKB4

Pin Configuration

SOIC/TSSOP Top View

REF 1

CLKA1 2

CLKA2 3 VDD 4 GND 5

CLKB1 6 CLKB2 7
16 CLKOUT 15 CLKA4
14 CLKA3 13 VDD 12 GND 11 CLKB4 10 CLKB3 9 S1

CLK2 CLK1 GND

SOIC/TSSOP

Top View

CLKOUT CLK4 VDD CLK3

Table Pin Description for MPC962309

Signal

REF1

Input reference frequency, 5 V-tolerant input

CLKA12

Buffered clock output, Bank A

CLKA22

Buffered clock output, Bank A

V supply

Ground

CLKB12

Buffered clock output, Bank B

CLKB22

Buffered clock output, Bank B

Select input, bit 2

Select input, bit 1

CLKB32
Table Ordering Information

MPC962305D-1 MPC962305D-1R2 MPC962305D-1H MPC962305D-1HR2 MPC962305DT-1H MPC962305DT-1HR2 MPC962309D-1 MPC962309D-1R2 MPC962309D-1H MPC962309D-1HR2 MPC962309DT-1H MPC962309DT-1HR2
Ordering Code

Package Type 8-pin 150-mil SOIC 8-pin 150-mil SOIC-Tape and Reel 8-pin 150-mil SOIC 8-pin 150-mil SOIC-Tape and Reel 8-pin 150-mil TSSOP 8-pin 150-mil TSSOP-Tape and Reel 16-pin 150-mil SOIC 16-pin 150-mil SOIC-Tape and Reel 16-pin 150-mil SOIC 16-pin 150-mil SOIC-Tape and Reel 16-pin 4.4-mm TSSOP 16-pin 4.4-mm TSSOP-Tape and Reel

Freescale Semiconductor, Inc...

TIMING SOLUTIONS

For More Informat6ion On This Product, Go to:

MOTOROLA

Freescale Semiconductor, Inc...

Freescale Semiconductor, Inc.

MPC962305 MPC962309

PACKAGE DIMENSIONS

D SUFFIX 8-LEAD SOIC PACKAGE

CASE 751-06 ISSUE T

SEATING PLANE

M C B S A S

NOTES DIMENSIONING AND TOLERANCING PER ASME Y14.5M, DIMENSIONS ARE IN MILLIMETER. DIMENSION D AND E DO NOT INCLUDE MOLD PROTRUSION. MAXIMUM MOLD PROTRUSION PER SIDE. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION.

MILLIMETERS

DIM MIN MAX

D SUFFIX

STYLE 1 PIN EMITTER COLLECTOR

STYLE 2 PIN COLLECTOR, DIE, #1 COLLECTOR, #1

STYLE 4 PIN ANODE

COLLECTOR EMITTER

COLLECTOR, #2 COLLECTOR, #2

IS3. SDURAEIN,K#2

DRAIN, #2

ANODE

EMITTER BASE EMITTER

PIN'S NUMBER

BASE, #2 EMITTER, #2 BASE, #1

EMITTAER, #1

GATE, #2

SOURCE, #2

GATE, #1

SO0U.2RC5E, #1

ANODE COMMON CATHODE

STYLE 5 PIN

DRAI1N

STY1PL6IEN

SOURCE

STYLE 7 PIN INPUT

M STTYPLAIEN 81B:. COLLECTOR, DIE #1

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Datasheet ID: MPC962305D-1H 635584