MPC961PFA

MPC961PFA Datasheet


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MPC961PFA MPC961PFA MPC961PFA (pdf)
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MOTOROLA

Freescale Semiconductor, Inc.

SEMICONDUCTOR TECHNICAL DATA

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Freescale Semiconductor, Inc...

Low Voltage Zero Delay Buffer

The MPC961 is a 2.5V or 3.3V compatible, 1:18 PLL based zero delay buffer. With output frequencies of up to 200MHz, output skews of 150ps the device meets the needs of the most demanding clock tree applications.
• Fully Integrated PLL
• Up to 200MHz I/O Frequency
• LVCMOS Outputs
• Outputs Disable in High Impedance
• LVPECL Reference Clock Options
• LQFP Packaging
• ±50ps Jitter
• 150ps Output Skews

The MPC961 is offered with two different input configurations. The MPC961C offers an LVCMOS reference clock while the MPC961P offers an LVPECL reference clock.

When pulled high the OE pin will force all of the outputs except QFB into a high impedance state. Because the OE pin does not affect the QFB output, down stream clocks can be disabled without the internal PLL losing lock.

The MPC961 is fully 2.5V or 3.3V compatible and requires no external loop filter components. All control inputs accept LVCMOS compatible levels and the outputs provide low impedance LVCMOS outputs capable

W of driving terminated 50 transmission lines. For series terminated lines
the MPC961 can drive two lines per output giving the device an effective fanout of The device is packaged in a 32 lead LQFP package to provide the optimum combination of board density and performance.

PCLK

FB_IN

F_RANGE

VCC 50k

Ref PLL
100 200 MHz
50 100 MHz

OE 50k

MPC961P

LOW VOLTAGE ZERO DELAY BUFFER

FA SUFFIX LQFP PACKAGE

CASE

Q0 Q1 Q2 Q3 Q14 Q15 Q16 QFB

The MPC961P requires an external RC filter for the analog power supply pin VCCA. Please see applications section for details. Figure MPC961P Logic Diagram
04/01

Motorola, Inc. 2001

Freescale Semiconductor, Inc...

MPC961P

Freescale Semiconductor, Inc.
24 23 22 21 20 19 18 17

MPC961P
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FB_IN

VCCA

F_RANGE

PCLK

PCLK

Figure Pinout Top View
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Datasheet ID: MPC961PFA 635583