MPC9449FA

MPC9449FA Datasheet

Order Number MPC9449/D Rev 1, 08/2002

Part	Datasheet
MPC9449FA	MPC9449FA (pdf)

Related Parts	Information
MPC9449FAR2	MPC9449FAR2
MPC9449AE	MPC9449AE
MPC9449AC	MPC9449AC

PDF Datasheet Preview
MOTOROLA SEMICONDUCTOR TECHNICAL DATA 3.3V/2.5V 1:15 PECL/LVCMOS Clock Fanout Buffer MPC9449 The MPC9449 is a 3.3V or 2.5V compatible, 1:15 clock fanout buffer targeted for high performance clock tree applications. With output frequencies up to 200 MHz and output skews less than 200 ps the device meets the needs of the most demanding clock applications. Features • 15 LVCMOS compatible clock outputs 3.3V/2.5V 1:15 PECL/LVCMOS • Two selectable LVCMOS and one differential LVPECL compatible clock inputs CLOCK FANOUT BUFFER • Selectable output frequency divider divide-by-one and divide-by-two • Maximum clock frequency of 200 MHz • Maximum clock skew of 200 ps • High-impedance output control • 3.3V or 2.5V power supply • Drives up to 30 series terminated clock lines • Ambient temperature range to +85°C • 52 lead LQFP packaging • Supports clock distribution in networking, telecommunication and computing applications • Pin and function compatible to MPC949 FA SUFFIX 52 LEAD LQFP PACKAGE CASE 848D Functional Description The MPC9449 is specifically designed to distribute LVCMOS compatible clock signals up to a frequency of 200 MHz. The device has 15 identical outputs, organized in 4 output banks. Each output bank provides a retimed or frequency divided copy of the input signal with a near zero skew. The output buffer supports driving of terminated transmission lines on the incident edge each output is capable of driving either one parallel terminated or two series terminated transmission lines. Two selectable LVCMOS compatible clock inputs are available. This feature supports redundant differential clock sources. In addition, the MPC9449 accepts one differential PECL clock signal. The DSELx pins choose between division of the input reference frequency by one or two. The frequency divider can be set individually for each of the four output banks. Applying the OE control will force the outputs into high-impedance mode. All inputs have an internal pull-up or pull-down resistor preventing unused and open inputs from floating. The device supports a 2.5V or 3.3V power supply and an ambient temperature range of to +85°C. The MPC9449 is pin and function compatible but performance-enhanced to the MPC949. The device is packaged in a 52-lead LQFP package. Motorola, Inc. 2002 MPC9449 DSELA 0 VCC CCLK0 CCLK1 CCLK_SEL PCLK 1 PCLK_SEL DSELB DSELC 0 1 DSELD MR/OE QC0 NC 4039 38 37 36 35 34 33 32 31 30 29 28 2726 QC1 VCC QC2 GND

PDF Datasheet Preview

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA
3.3V/2.5V 1:15 PECL/LVCMOS Clock Fanout Buffer

MPC9449

The MPC9449 is a 3.3V or 2.5V compatible, 1:15 clock fanout buffer targeted for high performance clock tree applications. With output frequencies up to 200 MHz and output skews less than 200 ps the device meets the needs of the most demanding clock applications.

Features
• 15 LVCMOS compatible clock outputs
3.3V/2.5V 1:15 PECL/LVCMOS
• Two selectable LVCMOS and one differential LVPECL compatible clock inputs

CLOCK FANOUT BUFFER
• Selectable output frequency divider divide-by-one and divide-by-two
• Maximum clock frequency of 200 MHz
• Maximum clock skew of 200 ps
• High-impedance output control
• 3.3V or 2.5V power supply
• Drives up to 30 series terminated clock lines
• Ambient temperature range to +85°C
• 52 lead LQFP packaging
• Supports clock distribution in networking, telecommunication and computing applications
• Pin and function compatible to MPC949

FA SUFFIX 52 LEAD LQFP PACKAGE

CASE 848D

Functional Description The MPC9449 is specifically designed to distribute LVCMOS
compatible clock signals up to a frequency of 200 MHz. The device has 15 identical outputs, organized in 4 output banks. Each output bank provides a retimed or frequency divided copy of the input signal with a near zero skew. The output buffer supports driving of terminated transmission lines on the incident edge each output is capable of driving either one parallel terminated or two series terminated transmission lines.

Two selectable LVCMOS compatible clock inputs are available. This feature supports redundant differential clock sources. In addition, the MPC9449 accepts one differential PECL clock signal. The DSELx pins choose between division of the input reference frequency by one or two. The frequency divider can be set individually for each of the four output banks. Applying the OE control will force the outputs into high-impedance mode.

All inputs have an internal pull-up or pull-down resistor preventing unused and open inputs from floating. The device supports a 2.5V or 3.3V power supply and an ambient temperature range of to +85°C. The MPC9449 is pin and function compatible but performance-enhanced to the MPC949. The device is packaged in a 52-lead LQFP package.

Motorola, Inc. 2002

MPC9449

DSELA
0 VCC

CCLK0

CCLK1

CCLK_SEL

PCLK
1 PCLK_SEL

DSELB DSELC
0 1 DSELD

MR/OE

QC0 NC
4039 38 37 36 35 34 33 32 31 30 29 28 2726

QC1 VCC

QC2 GND

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived MPC9449FA Datasheet file may be downloaded here without warranties.

Datasheet ID: MPC9449FA 635578