MPC9446AC

MPC9446AC Datasheet

MPC9446 Rev. 3, 08/2005

Part	Datasheet
MPC9446AC	MPC9446AC (pdf)

Related Parts	Information
MPC9446FAR2	MPC9446FAR2
MPC9446FA	MPC9446FA

PDF Datasheet Preview
Freescale Semiconductor Technical Data V and V LVCMOS Clock Fanout Buffer MPC9446 The MPC9446 is a V and V compatible 1:10 clock distribution buffer designed for low-voltage mid-range to high-performance telecom, networking and computing applications. Both V, V and dual supply voltages are supported for mixed-voltage applications. The MPC9446 offers 10 low-skew outputs and 2 selectable inputs for clock redundancy. The outputs are configurable and support 1:1 and 1:2 output to input frequency ratios. The MPC9446 is specified for the extended temperature range of to 85°C. LOW VOLTAGE SINGLE OR DUAL SUPPLY V AND V LVCMOS CLOCK DISTRIBUTION BUFFER • Configurable 10 outputs LVCMOS clock distribution buffer • Compatible to single, dual and mixed V/2.5 V voltage supply • Wide range output clock frequency up to 250 MHz • Designed for mid-range to high-performance telecom, networking and computer applications • Supports applications requiring clock redundancy • Maximum output skew of 200 ps 150 ps within one bank • Selectable output configurations per output bank • Tristable outputs • 32-lead LQFP package • 32-lead Pb-free package available • Ambient operating temperature range of to 85°C FA SUFFIX 32-LEAD LQFP PACKAGE CASE 873A-04 AC SUFFIX 32-LEAD LQFP PACKAGE Pb-FREE PACKAGE CASE 873A-04 Functional Description The MPC9446 is a full static fanout buffer design supporting clock frequencies up to 250 MHz. The signals are generated and retimed on-chip to ensure minimal skew between the three output banks. Two independent LVCMOS compatible clock inputs are available. This feature supports redundant clock sources or the addition of a test clock into the system design. Each of the three output banks can be individually supplied by V or V supporting mixed voltage applications. The FSELx pins choose between division of the input reference frequency by one or two. The frequency divider can be set individually for each of the three output banks. The MPC9446 can be rese,t and the outputs are disabled by deasserting the MR/OE pin logic high state . Asserting MR/OE will enable the outputs. All inputs accept LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 transmission lines. Please consult the MPC9456 specification for a 1:10 mixed voltage buffer with LVPECL compatible inputs. For series terminated transmission lines, each of the MPC9446 outputs can drive one or two traces giving the devices an effective fanout of The device is packaged in a 7x7 mm2 32-lead LQFP package. Freescale Semiconductor, Inc., All rights reserved. VCC 25k Bank A CCLK0 CCLK1 CLK ÷ 2 CCLK_SEL 25k Bank B 1 QB2 FSELA 25k FSELB 25k FSELC 25k MR/OE 25k Bank C Figure MPC9446 Logic Diagram GND QB0 VCCB QB1 GND QB2 VCCB VCCC VCCA QA2 GND QA1 VCCA QA0 GND MR/OE 24 23 22 21 20 19 18 17 MPC9446 12345678 VCCB is internally connected to VCC QC3 GND QC2 VCCC QC1 GND QC0 VCCC CCLK_SEL VCC CCLK0 CCLK1 FSELA FSELB FSELC Figure Pinout 32-Lead Package Pinout Top View MPC9446 2

PDF Datasheet Preview

Freescale Semiconductor Technical Data

V and V LVCMOS Clock Fanout Buffer

MPC9446

The MPC9446 is a V and V compatible 1:10 clock distribution buffer designed for low-voltage mid-range to high-performance telecom, networking and computing applications. Both V, V and dual supply voltages are supported for mixed-voltage applications. The MPC9446 offers 10 low-skew outputs and 2 selectable inputs for clock redundancy. The outputs are configurable and support 1:1 and 1:2 output to input frequency ratios. The MPC9446 is specified for the extended temperature range of to 85°C.

LOW VOLTAGE SINGLE OR DUAL SUPPLY V AND V

LVCMOS CLOCK DISTRIBUTION BUFFER
• Configurable 10 outputs LVCMOS clock distribution buffer
• Compatible to single, dual and mixed V/2.5 V voltage supply
• Wide range output clock frequency up to 250 MHz
• Designed for mid-range to high-performance telecom, networking
and computer applications
• Supports applications requiring clock redundancy
• Maximum output skew of 200 ps 150 ps within one bank
• Selectable output configurations per output bank
• Tristable outputs
• 32-lead LQFP package
• 32-lead Pb-free package available
• Ambient operating temperature range of to 85°C

FA SUFFIX 32-LEAD LQFP PACKAGE

CASE 873A-04

AC SUFFIX 32-LEAD LQFP PACKAGE

Pb-FREE PACKAGE CASE 873A-04

Functional Description

The MPC9446 is a full static fanout buffer design supporting clock frequencies up to 250 MHz. The signals are generated and retimed on-chip to ensure minimal skew between the three output banks. Two independent LVCMOS compatible clock inputs are available. This feature supports redundant clock sources or the addition of a test clock into the system design. Each of the three output banks can be individually supplied by V or V supporting mixed voltage applications. The FSELx pins choose between division of the input reference frequency by one or two. The frequency divider can be set individually for each of the three output banks. The MPC9446 can be rese,t and the outputs are disabled by deasserting the MR/OE pin logic high state . Asserting MR/OE will enable the outputs.

All inputs accept LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 transmission lines. Please consult the MPC9456 specification for a 1:10 mixed voltage buffer with LVPECL compatible inputs. For series terminated transmission lines, each of the MPC9446 outputs can drive one or two traces giving the devices an effective fanout of The device is packaged in a 7x7 mm2 32-lead LQFP package.

Freescale Semiconductor, Inc., All rights reserved.

VCC 25k

Bank A

CCLK0

CCLK1

CLK ÷ 2

CCLK_SEL 25k

Bank B
1 QB2

FSELA 25k

FSELB 25k

FSELC 25k

MR/OE 25k

Bank C

Figure MPC9446 Logic Diagram

GND QB0 VCCB QB1 GND QB2 VCCB VCCC

VCCA QA2 GND QA1 VCCA QA0 GND MR/OE
24 23 22 21 20 19 18 17

MPC9446
12345678

VCCB is internally connected to VCC

QC3 GND QC2 VCCC QC1 GND QC0 VCCC

CCLK_SEL VCC

CCLK0 CCLK1 FSELA FSELB FSELC

Figure Pinout 32-Lead Package Pinout Top View

MPC9446 2

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Datasheet ID: MPC9446AC 635575