MPC9443AE
MPC9443AE Datasheet
Order number MPC9443 Rev 3, 06/2004
| Part | Datasheet |
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MPC9443AE |
MPC9443AE (pdf) |
| Related Parts | Information |
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MPC9443FA |
MPC9443FA |
| PDF Datasheet Preview |
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| MOTOROLA SEMICONDUCTOR TECHNICAL DATA V and V LVCMOS Clock Fanout Buffer MPC9443 The MPC9443 is a V and V compatible 1:16 clock distribution buffer designed for low-voltage high-performance telecom, networking and computing applications. The device supports V, V and dual supply voltage mixed-voltage applications. The MPC9443 offers 16 low-skew outputs which are divided into 4 individually configurable banks. Each output bank can be individually supplied by V or V, individually set to run at 1X or 1/2X of the input clock frequency or be disabled logic low output state . Two selectable LVPECL compatible inputs support differential clock distribution systems. In addition, one selectable LVCMOS input is provided for LVCMOS clock distribution systems. The MPC9443 is specified for the extended temperature range of to +85°C. LOW VOLTAGE SUPPLY V AND V LVCMOS CLOCK FANOUT BUFFER • Configurable 16 outputs LVCMOS clock distribution buffer • Compatible to single, dual and mixed V / V voltage supply • Output clock frequency up to 350 MHz • Designed for high-performance telecom, networking and computer applications • Supports applications requiring clock redundancy • Max. output skew of 250 ps 125 ps within one bank • Selectable output configurations per output bank • Individually per-bank high-impedance tristate • Output disable stop in logic low state control • 48 ld LQFP package • Ambient operating temperature range of to 85°C SCALE 2:1 FA SUFFIX 48-LEAD LQFP PACKAGE CASE 932-03 Functional Description The MPC9443 is a full static design supporting clock frequencies up to 350 MHz. The signals are generated and retimed on-chip to ensure minimal skew between the four output banks. Two independent LVPECL compatible clock inputs are available. This feature supports redundant differential clock sources. In addition, the MPC9443 supports single-ended LVCMOS clock distribution systems. Each of the four output banks can be individually supplied by V or V, supporting mixed voltage applications. The FSELx pins choose between division of the input reference frequency by one or two. The frequency divider can be set individually for each output bank. The MPC9443 output banks are in high-impedance state by deasserting the OEN pins. Asserting OEN will the enable output banks. Please see Table Output HighImpedance Control OEN for details. The outputs can be synchronously stopped logic low state . The outputs provide LVCMOS compatible levels with the capability to drive terminated 50 transmission lines. For series terminated transmission lines, each of the MPC9443 outputs can drive one or two traces giving the devices an effective fanout of 1:32 at VCC = V. The device is packaged in a 7x7 mm2 48-lead LQFP package. Motorola, Inc. 2004 MPC9443 PCLK0 PULLDOWN PCLK0 PULLUP PCLK1 PULLDOWN BANK A QA0 QA1 PCLK1 PULLUP CLK ÷ 2 TCLK PULLDOWN PCLK_SEL TCLK_SEL PULLDOWN FSELA FSELB FSELC FSELD PULLDOWN BANK B QB0 0 QB1 1 QB2 BANK C CLK_STOP PULLDOWN BANK D QD1 QD2 1 PULLDOWN PULLDOWN |
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