MPC93R51FA

MPC93R51FA Datasheet

MPC93R51 Rev. 4, 1/2005

Part	Datasheet
MPC93R51FA	MPC93R51FA (pdf)

Related Parts	Information
MPC93R51AC	MPC93R51AC

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Freescale Semiconductor Technical Data Low Voltage PLL Clock Driver The MPC93R51 is a V compatible, PLL based clock generator targeted for high performance clock distribution systems. With output frequencies of up to 240 MHz and a maximum output skew of 150 ps, the MPC93R51 is an ideal solution for the most demanding clock tree designs. The device offers 9 low skew clock outputs, each is configurable to support the clocking needs of the various high-performance microprocessors including the PowerQuicc II integrated communication microprocessor. The devices employ a fully differential PLL design to minimize cycle-to-cycle and long-term jitter. MPC93R51 LOW VOLTAGE V PLL CLOCK GENERATOR • 9 outputs LVCMOS PLL clock generator • MHz output frequency range • Fully integrated PLL • Compatible to various microprocessors such as PowerQuicc II • Supports networking, telecommunications and computer applications • Configurable outputs divide-by-2, 4 and 8 of VCO frequency • LVPECL and LVCMOS compatible inputs • External feedback enables zero-delay configurations • Output enable/disable and static test mode PLL enable/disable • Low skew characteristics maximum 150 ps output-to-output • Cycle-to-cycle jitter max. 22 ps RMS • 32-lead LQFP package • 32-lead Pb-free Package Available • Ambient Temperature Range 0°C to +70°C • Pin & Function Compatible with the MPC951 FA SUFFIX 32-LEAD LQFP PACKAGE CASE 873A-03 AC SUFFIX 32-LEAD LQFP PACKAGE Pb-FREE PACKAGE CASE 873A-03 Functional Description The MPC93R51 utilizes PLL technology to frequency and phase lock its outputs onto an input reference clock. Normal operation of the MPC93R51 requires a connection of one of the device outputs to the EXT_FB input to close the PLL feedback path. The reference clock frequency and the output divider for the feedback path determine the VCO frequency. Both must be selected to match the VCO frequency range. With available output dividers of divide-by-4 and divide-by-8, the internal VCO of the MPC93R51 is running at either 4x or 8x of the reference clock frequency. The frequency of the QA, QB, QC and QD outputs is either the one half, one fourth or one eighth of the selected VCO frequency and can be configured for each output bank using the FSELA, FSELB, FSELC and FSELD pins, respectively. The available output to input frequency ratios are 4:1, 2:1, 1:1, 1:2 and The REF_SEL pin selects the differential LVPECL PCLK and PCLK or the LVCMOS compatible reference input TCLK . The MPC93R51 also provides a static test mode when the PLL enable pin PLL_EN is pulled to logic low state. In test mode, the selected input reference clock is routed directly to the output dividers bypassing the PLL. The test mode is intended for system diagnostics, test and debug purposes. This test mode is fully static and the minimum clock frequency specification does not apply. The outputs can be disabled by deasserting the OE pin logic high state . In PLL mode, deasserting OE causes the PLL to loose lock due to no feedback signal presence at EXT_FB. Asserting OE will enable the outputs and close the phase locked loop, also enabling the PLL to recover to normal operation. The MPC93R51 is V compatible and requires no external loop filter components. All inputs except PCLK and PCLK accept LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 transmission lines. For series terminated transmission lines, each of the MPC93R51 outputs can drive one or two traces giving the devices an effective fanout of The device is packaged in a 7x7 mm2 32-lead LQFP package. Application Information The fully integrated PLL of the MPC93R51 allows the low skew outputs to lock onto a clock input and distribute it with essentially zero propagation delay to multiple components on the board. In zero-delay buffer mode, the PLL minimizes phase offset between the outputs and the reference signal. This document contains certain information on a new product. Specifications and information herein are subject to change without notice. Freescale Semiconductor, Inc., All rights reserved. Freescale Confidential Proprietary, NDA Required / Preliminary PCLK Pullup TCLK Pulldown REF_SEL Pulldown EXT_FB Pulldown 200 480 MHz PLL_EN Pullup FSELA FSELB FSELC FSELD Pulldown QC0 0 QD1 0 1 QD3 QD4 Pulldown OE The MPC93R51 requires an external RC filter for the analog power supply pin VCCA. Please see application section for details. Figure MPC93R51 Logic Diagram QC0 VCCO QC1 GND QD0 VCCO QD1 GND MPC93R51 2 GND QB VCCO QA GND TCLK PLL_EN REF_SEL 24 23 22 21 20 19 18 17 MPC93R51 12345678 QD2 VCCO QD3 GND QD4 VCCO OE PCLK

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Freescale Semiconductor Technical Data

Low Voltage PLL Clock Driver

The MPC93R51 is a V compatible, PLL based clock generator targeted for high performance clock distribution systems. With output frequencies of up to 240 MHz and a maximum output skew of 150 ps, the MPC93R51 is an ideal solution for the most demanding clock tree designs. The device offers 9 low skew clock outputs, each is configurable to support the clocking needs of the various high-performance microprocessors including the PowerQuicc II integrated communication microprocessor. The devices employ a fully differential PLL design to minimize cycle-to-cycle and long-term jitter.

MPC93R51

LOW VOLTAGE V PLL CLOCK GENERATOR
• 9 outputs LVCMOS PLL clock generator
• MHz output frequency range
• Fully integrated PLL
• Compatible to various microprocessors such as PowerQuicc II
• Supports networking, telecommunications and computer applications
• Configurable outputs divide-by-2, 4 and 8 of VCO frequency
• LVPECL and LVCMOS compatible inputs
• External feedback enables zero-delay configurations
• Output enable/disable and static test mode PLL enable/disable
• Low skew characteristics maximum 150 ps output-to-output
• Cycle-to-cycle jitter max. 22 ps RMS
• 32-lead LQFP package
• 32-lead Pb-free Package Available
• Ambient Temperature Range 0°C to +70°C
• Pin & Function Compatible with the MPC951

FA SUFFIX 32-LEAD LQFP PACKAGE

CASE 873A-03

AC SUFFIX 32-LEAD LQFP PACKAGE

Pb-FREE PACKAGE CASE 873A-03

Functional Description

The MPC93R51 utilizes PLL technology to frequency and phase lock its outputs onto an input reference clock. Normal operation of the MPC93R51 requires a connection of one of the device outputs to the EXT_FB input to close the PLL feedback path. The reference clock frequency and the output divider for the feedback path determine the VCO frequency. Both must be selected to match the VCO frequency range. With available output dividers of divide-by-4 and divide-by-8, the internal VCO of the MPC93R51 is running at either 4x or 8x of the reference clock frequency. The frequency of the QA, QB, QC and QD outputs is either the one half, one fourth or one eighth of the selected VCO frequency and can be configured for each output bank using the FSELA, FSELB, FSELC and FSELD pins, respectively. The available output to input frequency ratios are 4:1, 2:1, 1:1, 1:2 and The REF_SEL pin selects the differential LVPECL PCLK and PCLK or the LVCMOS compatible reference input TCLK . The MPC93R51 also provides a static test mode when the PLL enable pin PLL_EN is pulled to logic low state. In test mode, the selected input reference clock is routed directly to the output dividers bypassing the PLL. The test mode is intended for system diagnostics, test and debug purposes. This test mode is fully static and the minimum clock frequency specification does not apply. The outputs can be disabled by deasserting the OE pin logic high state . In PLL mode, deasserting OE causes the PLL to loose lock due to no feedback signal presence at EXT_FB. Asserting OE will enable the outputs and close the phase locked loop, also enabling the PLL to recover to normal operation. The MPC93R51 is V compatible and requires no external loop filter components. All inputs except PCLK and PCLK accept LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 transmission lines. For series terminated transmission lines, each of the MPC93R51 outputs can drive one or two traces giving the devices an effective fanout of The device is packaged in a 7x7 mm2 32-lead LQFP package.

Application Information

The fully integrated PLL of the MPC93R51 allows the low skew outputs to lock onto a clock input and distribute it with essentially zero propagation delay to multiple components on the board. In zero-delay buffer mode, the PLL minimizes phase offset between the outputs and the reference signal.

This document contains certain information on a new product. Specifications and information herein are subject to change without notice.

Freescale Semiconductor, Inc., All rights reserved.

Freescale Confidential Proprietary, NDA Required / Preliminary

PCLK

Pullup

TCLK Pulldown

REF_SEL Pulldown

EXT_FB Pulldown
200 480 MHz

PLL_EN Pullup

FSELA FSELB FSELC FSELD

Pulldown

QC0 0

QD1 0
1 QD3

QD4 Pulldown OE

The MPC93R51 requires an external RC filter for the analog power supply pin VCCA. Please see application section for details.

Figure MPC93R51 Logic Diagram

QC0 VCCO QC1 GND QD0 VCCO QD1 GND

MPC93R51 2

GND QB

VCCO QA

GND TCLK PLL_EN REF_SEL
24 23 22 21 20 19 18 17

MPC93R51
12345678

QD2 VCCO QD3 GND QD4 VCCO OE PCLK

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Datasheet ID: MPC93R51FA 635568