MPC93H52FA

MPC93H52FA Datasheet

MPC93H52 Rev. 5, 1/2005

Part	Datasheet
MPC93H52FA	MPC93H52FA (pdf)

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Freescale Semiconductor Technical Data V 1:11 LVCMOS Zero Delay Clock Generator MPC93H52 The MPC93H52 is a V compatible, 1:11 PLL based clock generator targeted for high performance clock tree applications. With output frequencies up to 240 MHz and output skews lower than 200 ps the device meets the needs of most demanding clock applications. • Configurable 11 outputs LVCMOS PLL clock generator • Fully integrated PLL • Wide range of output clock frequency of MHz to 240 MHz • Multiplication of the input reference clock frequency by 3, 2, 1, 3÷2, 2÷3, 1÷3 and 1÷2 • V LVCMOS compatible • Maximum output skew of 200 ps • Supports zero-delay applications • Designed for high-performance telecom, networking and computing applications • 32-lead LQFP package • 32-lead Pb-free Package Available • Ambient Temperature Range 0°C to +70°C • Pin and function compatible to the MPC952 LOW VOLTAGE V LVCMOS 1:11 CLOCK GENERATOR FA SUFFIX 32-LEAD LQFP PACKAGE CASE 873A-03 AC SUFFIX 32-LEAD LQFP PACKAGE Pb-FREE PACKAGE CASE 873A-03 Functional Description The MPC93H52 is a fully V compatible PLL clock generator and clock driver. The device has the capability to generate output clock signals of to 240 MHz from external clock sources. The internal PLL is optimized for its frequency range and does not require external lock filter components. One output of the MPC93H52 has to be connected to the PLL feedback input FB_IN to close the external PLL feedback path. The output divider of this output setting determines the PLL frequency multiplication factor. This multiplication factor, F_RANGE, and the reference clock frequency must be selected to situate the VCO in its specified lock range. The frequency of the clock outputs can be configured individually for all three output banks by the FSELx pins supporting systems with different but phase-aligned clock frequencies. The PLL of the MPC93H52 minimizes the propagation delay and, therefore, supports zero-delay applications. All inputs and outputs are LVCMOS compatible. The outputs are optimized to drive parallel terminated 50 transmission lines. Alternatively, each output can drive up to two series terminated transmission lines giving the device an effective fanout of The device also supports output high-impedance disable and a PLL bypass mode for static system test and diagnosis. The MPC93H52 is package in a 32-lead LQFP. This document contains certain information on a new product. Specifications and information herein are subject to change without notice. Freescale Semiconductor, Inc., All rights reserved. Freescale Confidential Proprietary, NDA Required / Preliminary CCLK 1 Bank A CCLK VCO 0 FB_IN PLL_EN FB 200 480 MHz F_RANGE FSELA Bank B QB0 1 QB1 0 QB2 FSELB FSELC MR/OE POWER-ON RESET Bank C all input resistors have a value of 25 Figure MPC93H52 Logic Diagram 24 23 22 21 20 19 18 17 MPC93H52 VCCA PLL_EN 12345678 FB_IN CCLK

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Freescale Semiconductor Technical Data

V 1:11 LVCMOS Zero Delay Clock Generator

MPC93H52

The MPC93H52 is a V compatible, 1:11 PLL based clock generator targeted for high performance clock tree applications. With output frequencies up to 240 MHz and output skews lower than 200 ps the device meets the needs of most demanding clock applications.
• Configurable 11 outputs LVCMOS PLL clock generator
• Fully integrated PLL
• Wide range of output clock frequency of MHz to 240 MHz
• Multiplication of the input reference clock frequency by 3, 2, 1, 3÷2, 2÷3, 1÷3
and 1÷2
• V LVCMOS compatible
• Maximum output skew of 200 ps
• Supports zero-delay applications
• Designed for high-performance telecom, networking and computing
applications
• 32-lead LQFP package
• 32-lead Pb-free Package Available
• Ambient Temperature Range 0°C to +70°C
• Pin and function compatible to the MPC952

LOW VOLTAGE V LVCMOS 1:11 CLOCK GENERATOR

FA SUFFIX 32-LEAD LQFP PACKAGE

CASE 873A-03

AC SUFFIX 32-LEAD LQFP PACKAGE

Pb-FREE PACKAGE CASE 873A-03

Functional Description

The MPC93H52 is a fully V compatible PLL clock generator and clock driver. The device has the capability to generate output clock signals of to 240 MHz from external clock sources. The internal PLL is optimized for its frequency range and does not require external lock filter components. One output of the MPC93H52 has to be connected to the PLL feedback input FB_IN to close the external PLL feedback path. The output divider of this output setting determines the PLL frequency multiplication factor. This multiplication factor, F_RANGE, and the reference clock frequency must be selected to situate the VCO in its specified lock range. The frequency of the clock outputs can be configured individually for all three output banks by the FSELx pins supporting systems with different but phase-aligned clock frequencies.

The PLL of the MPC93H52 minimizes the propagation delay and, therefore, supports zero-delay applications. All inputs and outputs are LVCMOS compatible. The outputs are optimized to drive parallel terminated 50 transmission lines. Alternatively, each output can drive up to two series terminated transmission lines giving the device an effective fanout of

The device also supports output high-impedance disable and a PLL bypass mode for static system test and diagnosis. The MPC93H52 is package in a 32-lead LQFP.

This document contains certain information on a new product. Specifications and information herein are subject to change without notice.

Freescale Semiconductor, Inc., All rights reserved.

Freescale Confidential Proprietary, NDA Required / Preliminary

CCLK 1

Bank A

CCLK

VCO 0

FB_IN PLL_EN

FB 200 480 MHz

F_RANGE FSELA

Bank B QB0
1 QB1
0 QB2

FSELB FSELC MR/OE

POWER-ON RESET

Bank C
all input resistors have a value of 25

Figure MPC93H52 Logic Diagram
24 23 22 21 20 19 18 17

MPC93H52

VCCA

PLL_EN
12345678

FB_IN

CCLK

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Datasheet ID: MPC93H52FA 635567