MPC9315FA

MPC9315FA Datasheet

MPC9315 Rev. 4, 08/2005

Part	Datasheet
MPC9315FA	MPC9315FA (pdf)

Related Parts	Information
MPC9315AC	MPC9315AC

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Freescale Semiconductor Technical Data V and V CMOS PLL Clock Generator and Driver MPC9315 The MPC9315 is a V and V compatible, PLL based clock generator designed for low-skew clock distribution in low-voltage mid-range to high-performance telecom, networking and computing applications. The MPC9315 offers 8 low-skew outputs and 2 selectable inputs for clock redundancy. The outputs are configurable and support 1:1, 2:1, 4:1, 1:2 and 1:4 output to input frequency ratios. In addition, a selectable output 180° phase control supports advanced clocking schemes with inverted clock signals. The MPC9315 is specified for the extended temperature range of to +85°C. LOW VOLTAGE V AND V PLL CLOCK GENERATOR • Configurable 8 outputs LVCMOS PLL clock generator • Compatible to various microprocessors such as PowerQUICC I and II • Wide range output clock frequency of to 160 MHz • V and V CMOS compatible • Designed for mid-range to high-performance telecom, networking and computer applications • Fully integrated PLL supports spread spectrum clocking • Supports applications requiring clock redundancy • Max. output skew of 120 ps 80 ps within one bank • Selectable output configurations 1:1, 2:1, 4:1, 1:2, 1:4 frequency ratios • Two selectable LVCMOS clock inputs • External PLL feedback path and selectable feedback configuration • Tristable outputs • 32-Lead LQFP package • Ambient operating temperature range of -40 to +85°C • 32-Lead Pb-free package available FA SUFFIX 32-LEAD LQFP PACKAGE CASE 873A-04 AC SUFFIX 32-LEAD LQFP PACKAGE Pb-FREE PACKAGE CASE 873A-04 Functional Description The MPC9315 utilizes PLL technology to frequency and phase lock its outputs onto an input reference clock. Normal operation requires a connection of one of the device outputs to the selected feedback FB0 or FB1 input to close the PLL feedback path. The reference clock frequency and the output divider for the feedback path determine the VCO frequency. Both must be selected to match the VCO frequency range. With available output dividers of divide-by-1, divide-by-2 and divide-by-4, the internal VCO of the MPC9315 is running at either 1x, 2x or 4x of the reference clock frequency. The frequency of the QA, QB, QC output groups is either the equal, one half or one fourth of the selected VCO frequency and can be configured for each output bank using the FSELA, FSELB and FSELC pins, respectively. The available output to input frequency ratios are 4:1, 2:1, 1:1, 1:2 and The REF_SEL pin selects one of the two available LVCMOS compatible reference input CLK0 and CLK1 supporting clock redundant applications. The selectable feedback input pin allows the user to select different feedback configurations and input to output frequency ratios. The MPC9315 also provides a static test mode when the PLL supply pin VCCA is pulled to logic low state GND . In test mode, the selected input reference clock is routed directly to the output dividers bypassing the PLL. The test mode is intended for system diagnostics, test and debug purposes. This test mode is fully static and the minimum clock frequency specification does not apply. The outputs can be disabled by deasserting the OE pin logic high state . In PLL mode, deasserting OE causes the PLL to lose lock due to no feedback signal presence at FB0 or FB1. Asserting OE will enable the outputs and close the phase locked loop, also enabling the PLL to recover to normal operation. The MPC9315 is fully V and V compatible and requires no external loop filter components. All inputs accept LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 transmission lines. For series terminated transmission lines, each of the MPC9315 outputs can drive one or two traces giving the devices an effective fanout of The device is packaged in a 7x7 mm2 32-lead LQFP package. The fully integrated PLL of the MPC9315 allows the low skew outputs to lock onto a clock input and distribute it with essentially zero propagation delay to multiple components on the board. In zero-delay buffer mode, the PLL minimizes phase offset between the outputs and the reference signal. Freescale Semiconductor, Inc., All rights reserved. CLK0 CLK1 REF_SEL PULLDOWN 0 PULLDOWN 1 PULLDOWN FB0 FB1 FB_SEL FSELA PSELA FSELB FSELC OE PULLDOWN 0 PULLDOWN 1 PULLDOWN PULLDOWN PULLUP PULLUP PULLDOWN VCCA VCC 6 Ref PLL FB 75 160 MHz CLK÷2 CLK÷4 GND 6 Figure MPC9315 Logic Diagram BANK A BANK B QB0 QB1 QB2 BANK C QC0 GND QA1 QA0 VCC FSELC FSELB FSELA GND 24 23 22 21 20 19 18 17

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Freescale Semiconductor Technical Data

V and V CMOS PLL Clock Generator and Driver

MPC9315

The MPC9315 is a V and V compatible, PLL based clock generator designed for low-skew clock distribution in low-voltage mid-range to high-performance telecom, networking and computing applications. The MPC9315 offers 8 low-skew outputs and 2 selectable inputs for clock redundancy. The outputs are configurable and support 1:1, 2:1, 4:1, 1:2 and 1:4 output to input frequency ratios. In addition, a selectable output 180° phase control supports advanced clocking schemes with inverted clock signals. The MPC9315 is specified for the extended temperature range of to +85°C.

LOW VOLTAGE V AND V PLL CLOCK GENERATOR
• Configurable 8 outputs LVCMOS PLL clock generator
• Compatible to various microprocessors such as PowerQUICC I and II
• Wide range output clock frequency of to 160 MHz
• V and V CMOS compatible
• Designed for mid-range to high-performance telecom, networking and
computer applications
• Fully integrated PLL supports spread spectrum clocking
• Supports applications requiring clock redundancy
• Max. output skew of 120 ps 80 ps within one bank
• Selectable output configurations 1:1, 2:1, 4:1, 1:2, 1:4 frequency ratios
• Two selectable LVCMOS clock inputs
• External PLL feedback path and selectable feedback configuration
• Tristable outputs
• 32-Lead LQFP package
• Ambient operating temperature range of -40 to +85°C
• 32-Lead Pb-free package available

FA SUFFIX 32-LEAD LQFP PACKAGE

CASE 873A-04

AC SUFFIX 32-LEAD LQFP PACKAGE

Pb-FREE PACKAGE CASE 873A-04

Functional Description

The MPC9315 utilizes PLL technology to frequency and phase lock its outputs onto an input reference clock. Normal operation requires a connection of one of the device outputs to the selected feedback FB0 or FB1 input to close the PLL feedback path. The reference clock frequency and the output divider for the feedback path determine the VCO frequency. Both must be selected to match the VCO frequency range. With available output dividers of divide-by-1, divide-by-2 and divide-by-4, the internal VCO of the MPC9315 is running at either 1x, 2x or 4x of the reference clock frequency. The frequency of the QA, QB, QC output groups is either the equal, one half or one fourth of the selected VCO frequency and can be configured for each output bank using the FSELA, FSELB and FSELC pins, respectively. The available output to input frequency ratios are 4:1, 2:1, 1:1, 1:2 and The REF_SEL pin selects one of the two available LVCMOS compatible reference input CLK0 and CLK1 supporting clock redundant applications. The selectable feedback input pin allows the user to select different feedback configurations and input to output frequency ratios. The MPC9315 also provides a static test mode when the PLL supply pin VCCA is pulled to logic low state GND . In test mode, the selected input reference clock is routed directly to the output dividers bypassing the PLL. The test mode is intended for system diagnostics, test and debug purposes. This test mode is fully static and the minimum clock frequency specification does not apply. The outputs can be disabled by deasserting the OE pin logic high state . In PLL mode, deasserting OE causes the PLL to lose lock due to no feedback signal presence at FB0 or FB1. Asserting OE will enable the outputs and close the phase locked loop, also enabling the PLL to recover to normal operation. The MPC9315 is fully V and V compatible and requires no external loop filter components. All inputs accept LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 transmission lines. For series terminated transmission lines, each of the MPC9315 outputs can drive one or two traces giving the devices an effective fanout of The device is packaged in a 7x7 mm2 32-lead LQFP package.

The fully integrated PLL of the MPC9315 allows the low skew outputs to lock onto a clock input and distribute it with essentially zero propagation delay to multiple components on the board. In zero-delay buffer mode, the PLL minimizes phase offset between the outputs and the reference signal.

Freescale Semiconductor, Inc., All rights reserved.

CLK0 CLK1 REF_SEL

PULLDOWN 0

PULLDOWN 1

PULLDOWN

FB0 FB1

FB_SEL FSELA PSELA FSELB

FSELC OE

PULLDOWN 0

PULLDOWN 1

PULLDOWN

PULLDOWN PULLUP

PULLUP PULLDOWN

VCCA

VCC 6

Ref PLL

FB 75 160 MHz

CLK÷2

CLK÷4

GND 6

Figure MPC9315 Logic Diagram

BANK A

BANK B QB0

QB1 QB2

BANK C QC0

GND QA1 QA0 VCC FSELC FSELB FSELA GND
24 23 22 21 20 19 18 17

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Datasheet ID: MPC9315FA 635560