MPC9239FN

MPC9239FN Datasheet

MPC9239 Rev. 3, 08/2005

Part	Datasheet
MPC9239FN	MPC9239FN (pdf)

Related Parts	Information
MPC9239FA	MPC9239FA

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Freescale Semiconductor Technical Data 900 MHz Low Voltage LVPECL Clock Synthesizer MPC9239 The MPC9239 is a V compatible, PLL based clock synthesizer targeted for high performance clock generation in mid-range to high-performance telecom, networking, and computing applications. With output frequencies from MHz to 900 MHz and the support of differential LVPECL output signals the device meets the needs of the most demanding clock applications. 900 MHz LOW VOLTAGE CLOCK SYNTHESIZER • MHz to 900 MHz synthesized clock output signal • Differential LVPECL output • LVCMOS compatible control inputs • On-chip crystal oscillator for reference frequency generation • Alternative LVCMOS compatible reference input • V power supply • Fully integrated PLL • Minimal frequency overshoot • Serial 3-wire programming interface • Parallel programming interface for power-up • 28 PLCC and 32 LQFP packaging • 28-lead and 32-lead Pb-free package available • SiGe Technology • Ambient temperature range 0°C to + 70°C • Pin and function compatible to the MC12439 Functional Description FN SUFFIX 28-LEAD PLCC PACKAGE CASE 776-02 EI SUFFIX 28-LEAD PLCC PACKAGE Pb-FREE PACKAGE CASE 776-02 FA SUFFIX 32-LEAD LQFP PACKAGE CASE 873A-04 AC SUFFIX 32-LEAD LQFP PACKAGE Pb-FREE PACKAGE CASE 873A-04 The internal crystal oscillator uses the external quartz crystal as the basis of its frequency reference. The frequency of the internal crystal oscillator or external reference clock signal is multiplied by the PLL. The VCO within the PLL operates over a range of 800 to 1800 MHz. Its output is scaled by a divider that is configured by either the serial or parallel interfaces. The crystal oscillator frequency fXTAL, the PLL feedback-divider M and the PLL post-divider N determine the output frequency. The feedback path of the PLL is internal. The PLL adjusts the VCO output frequency to be M times the reference frequency by adjusting the VCO control voltage. Note that for some values of M either too high or too low the PLL will not achieve phase lock. The PLL will be stable if the VCO frequency is within the specified VCO frequency range 800 to 1800 MHz . The M-value must be programmed by the serial or parallel interface. The PLL post-divider N is configured through either the serial or the parallel interfaces, and can provide one of four division ratios 1, 2, 4, or This divider extends performance of the part while providing a 50% duty cycle. The output driver is driven differentially from the output divider, and is capable of driving a pair of transmission lines terminated 50 to VCC V. The positive supply voltage for the internal PLL is separated from the power supply for the core logic and output drivers to minimize noise induced jitter. The configuration logic has two sections serial and parallel. The parallel interface uses the values at the M[6:0] and N[1:0] inputs to configure the internal counters. It is recommended on system reset to hold the P_LOAD input LOW until power becomes valid. On the LOW-to-HIGH transition of P_LOAD, the parallel inputs are captured. The parallel interface has priority over the serial interface. Internal pullup resistors are provided on the M[6:0] and N[1:0] inputs prevent the LVCMOS compatible control inputs from floating. The serial interface centers on a twelve bit shift register. The shift register shifts once per rising edge of the S_CLOCK input. The serial input S_DATA must meet setup and hold timing as specified in the AC Characteristics section of this document. The configuration latches will capture the value of the shift register on the HIGH-to-LOW edge of the S_LOAD input. Refer to the programming section for more information. The TEST output reflects various internal node values, and is controlled by the T[2:0] bits in the serial data stream. In order to minimize the PLL jitter, it is recommended to avoid active signal on the TEST output. The PWR_DOWN pin, when asserted, will synchronously divide the fOUT by The power down sequence is clocked by the PLL reference clock, thereby causing the frequency reduction to happen relatively slowly. Upon de-assertion of the PWR_DOWN pin, the fOUT input will step back up to its programmed frequency in four discrete increments. Freescale Semiconductor, Inc., All rights reserved. XTAL_IN XTAL_OUT XTAL 1 10 20 MHz fREF_EXT PLL 800 1800 MHz XTAL_SEL VCC P_LOAD S_LOAD S_DATA S_CLOCK ÷0 TO ÷127 7-BIT M-DIVIDER M-LATCH LE BITS 11-5 N-LATCH BITS 3-4 12-BIT SHIFT REGISTER M[0:6] N[1:0] PWR_DOWN OE ÷16 1 OE TEST 3 T-LATCH BITS 0-2 Figure MPC9239 Logic Diagram

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Freescale Semiconductor Technical Data
900 MHz Low Voltage LVPECL Clock Synthesizer

MPC9239

The MPC9239 is a V compatible, PLL based clock synthesizer targeted for high performance clock generation in mid-range to high-performance telecom, networking, and computing applications. With output frequencies from MHz to 900 MHz and the support of differential LVPECL output signals the device meets the needs of the most demanding clock applications.
900 MHz LOW VOLTAGE CLOCK SYNTHESIZER
• MHz to 900 MHz synthesized clock output signal
• Differential LVPECL output
• LVCMOS compatible control inputs
• On-chip crystal oscillator for reference frequency generation
• Alternative LVCMOS compatible reference input
• V power supply
• Fully integrated PLL
• Minimal frequency overshoot
• Serial 3-wire programming interface
• Parallel programming interface for power-up
• 28 PLCC and 32 LQFP packaging
• 28-lead and 32-lead Pb-free package available
• SiGe Technology
• Ambient temperature range 0°C to + 70°C
• Pin and function compatible to the MC12439

Functional Description

FN SUFFIX 28-LEAD PLCC PACKAGE

CASE 776-02

EI SUFFIX 28-LEAD PLCC PACKAGE

Pb-FREE PACKAGE CASE 776-02

FA SUFFIX 32-LEAD LQFP PACKAGE

CASE 873A-04

AC SUFFIX 32-LEAD LQFP PACKAGE

Pb-FREE PACKAGE CASE 873A-04

The internal crystal oscillator uses the external quartz crystal as the basis of its frequency reference. The frequency of the internal crystal oscillator or external reference clock signal is multiplied by the PLL. The VCO within the PLL operates over a range of 800 to 1800 MHz. Its output is scaled by a divider that is configured by either the serial or parallel interfaces. The crystal oscillator frequency fXTAL, the PLL feedback-divider M and the PLL post-divider N determine the output frequency.

The feedback path of the PLL is internal. The PLL adjusts the VCO output frequency to be M times the reference frequency by adjusting the VCO control voltage. Note that for some values of M either too high or too low the PLL will not achieve phase lock. The PLL will be stable if the VCO frequency is within the specified VCO frequency range 800 to 1800 MHz . The M-value must be programmed by the serial or parallel interface.

The PLL post-divider N is configured through either the serial or the parallel interfaces, and can provide one of four division ratios 1, 2, 4, or This divider extends performance of the part while providing a 50% duty cycle. The output driver is driven differentially from the output divider, and is capable of driving a pair of transmission lines terminated 50 to VCC V. The positive supply voltage for the internal PLL is separated from the power supply for the core logic and output drivers to minimize noise induced jitter.

The configuration logic has two sections serial and parallel. The parallel interface uses the values at the M[6:0] and N[1:0] inputs to configure the internal counters. It is recommended on system reset to hold the P_LOAD input LOW until power becomes valid. On the LOW-to-HIGH transition of P_LOAD, the parallel inputs are captured. The parallel interface has priority over the serial interface. Internal pullup resistors are provided on the M[6:0] and N[1:0] inputs prevent the LVCMOS compatible control inputs from floating. The serial interface centers on a twelve bit shift register. The shift register shifts once per rising edge of the S_CLOCK input. The serial input S_DATA must meet setup and hold timing as specified in the AC Characteristics section of this document. The configuration latches will capture the value of the shift register on the HIGH-to-LOW edge of the S_LOAD input. Refer to the programming section for more information. The TEST output reflects various internal node values, and is controlled by the T[2:0] bits in the serial data stream. In order to minimize the PLL jitter, it is recommended to avoid active signal on the TEST output. The PWR_DOWN pin, when asserted, will synchronously divide the fOUT by The power down sequence is clocked by the PLL reference clock, thereby causing the frequency reduction to happen relatively slowly. Upon de-assertion of the PWR_DOWN pin, the fOUT input will step back up to its programmed frequency in four discrete increments.

Freescale Semiconductor, Inc., All rights reserved.

XTAL_IN XTAL_OUT

XTAL 1
10 20 MHz
fREF_EXT

PLL 800 1800 MHz

XTAL_SEL

VCC P_LOAD S_LOAD

S_DATA S_CLOCK
÷0 TO ÷127 7-BIT M-DIVIDER

M-LATCH LE

BITS 11-5

N-LATCH

BITS 3-4
12-BIT SHIFT REGISTER

M[0:6] N[1:0]

PWR_DOWN OE
÷16 1 OE

TEST 3

T-LATCH

BITS 0-2

Figure MPC9239 Logic Diagram

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Datasheet ID: MPC9239FN 635558