KMPC8560PX667LB

KMPC8560PX667LB Datasheet

Part	Datasheet
KMPC8560PX667LB	KMPC8560PX667LB (pdf)

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KMPC8560VT667LC	KMPC8560VT667LC
KMPC8560VT667LB	KMPC8560VT667LB
KMPC8560CPX667JB	KMPC8560CPX667JB
KMPC8560CVT667JB	KMPC8560CVT667JB
KMPC8560PX833LB	KMPC8560PX833LB
KMPC8560PX833LC	KMPC8560PX833LC
KMPC8560PXAQFB	KMPC8560PXAQFB
KMPC8560VTAQFB	KMPC8560VTAQFB
KMPC8560VT833LB	KMPC8560VT833LB
KMPC8560VT833LC	KMPC8560VT833LC
KMPC8560PX667LC	KMPC8560PX667LC
KMPC8560PX667JB	KMPC8560PX667JB

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Freescale Semiconductor Technical Data MPC8560 Integrated Processor Hardware Specifications The MPC8560 integrates a PowerPC processor core built on Power Architecture technology with system logic required for networking, telecommunications, and wireless infrastructure applications. The MPC8560 is a member of the PowerQUICC III family of devices that combine system-level support for industry-standard interfaces with processors that implement the embedded category of the Power Architecture technology. For functional characteristics of the processor, refer to the MPC8560 PowerQUICC III Integrated Communications Processor Reference Manual. To locate any published errata or updates for this document, contact your Freescale sales office. Freescale Semiconductor, Inc., All rights reserved. Overview The following section provides a high-level overview of the MPC8560 features. Figure 1 shows the major functional units within the MPC8560. DDR SDRAM GPIO 32b IRQs MPHY UTOPIAs MIIs, RMIIs TDMs I/Os Serial Interfaces TC - Layer Time Slot Assigner Time Slot Assigner DDR SDRAM Controller I2C Controller Local Bus Controller Programmable Interrupt Controller MCC FCC SCC SPI I2C Serial DMA I-Memory DPRAM RISC Engine Parallel I/O Baud Rate Generators Timers CPM Interrupt Controller e500 Coherency Module 256KB L2-Cache/ SRAM e500 Core 32 KB L1 I Cache 32 KB L1 D Cache Core Complex Bus OCeaN RapidIO Controller PCI Controller DMA Controller RapidIO-8 16 Gb/s PCI 64b 133 MHz 10/100/1000 MAC 10/100/1000 MAC MII, GMII, TBI, RTBI, RGMIIs Figure MPC8560 Block Diagram transactions Sleep mode support for self refresh SDRAM Supports auto refreshing On-the-fly power management using CKE signal Registered DIMM support Fast memory access via JTAG port 2.5-V SSTL2 compatible I/O • RapidIO interface unit 8-bit RapidIO I/O and messaging protocols Source-synchronous double data rate DDR interfaces Supports small type systems small domain, 8-bit device ID Supports four priority levels ordering within a level Reordering across priority levels Maximum data payload of 256 bytes per packet pacing support at the physical layer CRC protection for packets Supports atomic operations increment, decrement, set, and clear LVDS signaling • message unit One inbound data message structure inbox One outbound data message structure outbox Supports chaining and direct modes in the outbox Support of up to 16 packets per message Support of up to 256 bytes per packet and up to 4 Kbytes of data per message Supports one inbound doorbell message structure • Programmable interrupt controller PIC Programming model is compliant with the OpenPIC architecture Supports 16 programmable interrupt and processor task priority levels Supports 12 discrete external interrupts Supports 4 message interrupts with 32-bit messages Supports connection of an external interrupt controller such as the 8259 programmable interrupt controller Four global high resolution timers/counters that can generate interrupts Supports 22 other internal interrupt sources Supports fully nested interrupt delivery Interrupts can be routed to external pin for external processing Freescale Semiconductor Overview Interrupts can be routed to the e500 core’s standard or critical interrupt inputs Interrupt summary registers allow fast identification of interrupt source • I2C controller Two-wire interface Multiple master support Master or slave I2C mode support On-chip digital filtering rejects spikes on the bus • Boot sequencer Optionally loads configuration data from serial ROM at reset via the I2C interface Can be used to initialize configuration registers and/or memory Supports extended I2C addressing mode Data integrity checked with preamble signature and CRC • Local bus controller LBC Multiplexed 32-bit address and data operating at up to 166 MHz Eight chip selects support eight external slaves Up to eight-beat burst transfers The 32-, 16-, and 8-bit port sizes are controlled by an on-chip memory controller Three protocol engines available on a per chip select basis: General purpose chip select machine GPCM Three user programmable machines UPMs Dedicated single data rate SDRAM controller Parity support Default boot ROM chip select with configurable bus width 8-,16-, or 32-bit • Two three-speed 10/100/1Gb Ethernet controllers TSECs Dual IEEE 802.3u, 802.3x, 802.3z, 802.3ac, 802.3ab compliant controllers Support for different Ethernet physical interfaces 10/100/1Gb Mbps IEEE GMII 10/100 Mbps IEEE MII 10 Mbps IEEE MII 1000 Mbps IEEE 802.3z TBI 10/100/1Gb Mbps RGMII/RTBI Full- and half-duplex support Buffer descriptors are backward compatible with MPC8260 and MPC860T 10/100 programming models 9.6-Kbyte jumbo frame support RMON statistics support 2-Kbyte internal transmit and receive FIFOs Freescale Semiconductor Overview MII management interface for control and status Programmable CRC generation and checking Ability to force allocation of header information and buffer descriptors into L2 cache. • OCeaN switch fabric Four-port crossbar packet switch Reorders packets from a source based on priorities Reorders packets to bypass blocked packets Implements starvation avoidance algorithms Supports packets with payloads of up to 256 bytes • Integrated DMA controller Four-channel controller All channels accessible by both the local and remote masters Extended DMA functions advanced chaining and striding capability Support for scatter and gather transfers Misaligned transfer capability Interrupt on completed segment, link, list, and error Supports transfers to or from any local memory or I/O port Selectable hardware-enforced coherency snoop/no-snoop Ability to start and flow control each DMA channel from external 3-pin interface Ability to launch DMA from single write transaction • PCI/PCI-X controller PCI and PCI-X compatible 64- or 32-bit PCI port supports at 16 to 66 MHz 64-bit PCI-X support up to 133 MHz Host and agent mode support 64-bit dual address cycle DAC support PCI-X supports multiple split transactions Supports PCI-to-memory and memory-to-PCI streaming Memory prefetching of PCI read accesses Supports posting of processor-to-PCI and PCI-to-memory writes PCI 3.3-V compatible Selectable hardware-enforced coherency • Power management Fully static 1.2-V CMOS design with and 2.5-V I/O Supports power saving modes doze, nap, and sleep Employs dynamic power management, which automatically minimizes power consumption of blocks when they are idle. Freescale Semiconductor Electrical Characteristics • System performance monitor Supports eight 32-bit counters that count the occurrence of selected events Ability to count up to 512 counter-specific events Supports 64 reference events that can be counted on any of the 8 counters Supports duration and quantity threshold counting Burstiness feature that permits counting of burst events with a programmable time between bursts Triggering and chaining capability Ability to generate an interrupt on overflow • System access port Uses JTAG interface and a TAP controller to access entire system memory map Supports 32-bit accesses to configuration registers Supports cache-line burst accesses to main memory Supports large block 4-Kbyte uploads and downloads Supports continuous bit streaming of entire block for fast upload and download • IEEE Std 1149.1 -compliant, JTAG boundary scan • 783 FC-PBGA package 2 Electrical Characteristics This section provides the electrical specifications and thermal characteristics for the MPC8560. The MPC8560 is currently targeted to these specifications. Some of these specifications are independent of the I/O cell, but are included for a more complete reference. These are not purely I/O buffer design specifications. Overall DC Electrical Characteristics This section covers the ratings, conditions, and other characteristics. Absolute Maximum Ratings Table 1 provides the absolute maximum ratings. Table Absolute Maximum Ratings 1 Core supply voltage PLL supply voltage Characteristic For devices rated at 667 and 833 MHz For devices rated at 1 GHz For devices rated at 667 and 833 MHz For devices rated at 1 GHz Symbol VDD AVDD Max Value Unit Notes Freescale Semiconductor Electrical Characteristics Table Absolute Maximum Ratings 1 continued Characteristic Max Value Unit Notes DDR DRAM I/O voltage Three-speed Ethernet I/O voltage GVDD LVDD CPM, PCI/PCI-X, local bus, RapidIO, 10/100 Ethernet,MII management, DUART, system control and power management, I2C, and JTAG I/O voltage OVDD Items on the same line have no ordering requirement with respect to one another. Items on separate lines must be ordered sequentially such that voltage rails on a previous step must reach 90 percent of their value before the voltage rails on the current step reach 10 percent of theirs. Freescale Semiconductor Electrical Characteristics NOTE If the items on line 2 must precede items on line 1, please ensure that the delay will not exceed 500 ms and the power sequence is not done greater than once per day in production environment. NOTE From a system standpoint, if the I/O power supplies ramp prior to the VDD core supply, the I/Os on the MPC8560 may drive a logic one or zero during power-up. Recommended Operating Conditions Table 2 provides the recommended operating conditions for the MPC8560. Note that the values in Table 2 are the recommended and tested operating conditions. Proper device operation outside of these conditions is not guaranteed. Table Recommended Operating Conditions Characteristic Core supply voltage PLL supply voltage DDR DRAM I/O voltage Three-speed Ethernet I/O voltage For devices rated at 667 and 833 MHz For devices rated at 1 GHz For devices rated at 667 and 833 MHz For devices rated at 1 GHz AVDD GVDD LVDD CPM, PCI/PCI-X, local bus, RapidIO, 10/100 Ethernet, MII management, DUART, system control and power management, I2C, and JTAG I/O voltage Input voltage DDR DRAM signals DDR DRAM reference Three-speed Ethernet signals CPM, PCI/PCI-X, local bus, RapidIO, 10/100 Ethernet, MII management, DUART, SYSCLK, system control and power management, I2C, and JTAG signals Die-junction temperature OVDD MVIN MVREF LVIN OVIN Recommended Value V ± 60 mV V ± 50 mV V ± 60 mV V ± 50 mV V ± 125 mV V ± 165 mV V ± 125 mV V ± 165 mV GND to GVDD GND to GVDD/2 GND to LVDD GND to OVDD 0 to 105 Unit V Freescale Semiconductor Electrical Characteristics Figure 2 shows the undershoot and overshoot voltages at the interfaces of the MPC8560. G/L/OVDD + 20% G/L/OVDD + 5% G/L/OVDD GND V VIL GND V Not to Exceed 10% of tSYS1 Ordering information for the parts fully covered by this specification document is provided in Section “Part Numbers Fully Addressed by this Document.” Part Numbers Fully Addressed by this Document Table Part Numbering Nomenclature nnnn Product Part Code Identifier Temperature Range 1 Package 2 Processor Platform Frequency 3, 4 Frequency 8560 Blank = 0 to 105°C= -40 to 105°C PX = FC-PBGA 833 = 833 MHz L = 333 MHz VT = FC-PBGA 667 = 667 MHz J= 266 MHz Pb-free 8560 Blank = 0 to 105°C = to 105°C PX = FC-PBGA AQ = GHz VT = FC-PBGA Pb-free F = 333 MHz Notes 1.For Temperature Range=C, Processor Frequency is limited to 667 MHz. 2.See Section 14, “Package and Pin Listings” for more information on available package types. 3.Processor core frequencies supported by parts addressed by this specification only. Not all parts described in this specification support all core frequencies. The core must be clocked at a minimum frequency of 400 MHz. A device must not be used beyond the core frequency or platform frequency indicated on the device. Designers should use the maximum power value corresponding to the core and platform frequency grades indicated on the device. A lower maximum power value should not be assumed for design purposes even when running at a lower frequency. Freescale Semiconductor Part Marking Parts are marked as the example shown in Figure Device Nomenclature MPC8n5nnntppfffcr xAPTXWxLxYxYnWWA AMTMWMLMYYMWCWCACCC CYWCCWCLCAZ FC-PBGA is the 5-digit mask number. ATWLYYWWA is the traceability code. is the country of assembly. This space is left blank if parts are assembled in the United States. YWWLAZ is the assembly traceability code. Figure Part Marking for FC-PBGA Device Freescale Semiconductor Device Nomenclature THIS PAGE INTENTIONALLY LEFT BLANK Freescale Semiconductor THIS PAGE INTENTIONALLY LEFT BLANK

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Freescale Semiconductor

Technical Data

MPC8560 Integrated Processor Hardware Specifications

The MPC8560 integrates a PowerPC processor core built on Power Architecture technology with system logic required for networking, telecommunications, and wireless infrastructure applications. The MPC8560 is a member of the PowerQUICC III family of devices that combine system-level support for industry-standard interfaces with processors that implement the embedded category of the Power Architecture technology. For functional characteristics of the processor, refer to the MPC8560 PowerQUICC III Integrated Communications Processor Reference Manual.

To locate any published errata or updates for this document, contact your Freescale sales office.

Freescale Semiconductor, Inc., All rights reserved.

Overview

The following section provides a high-level overview of the MPC8560 features. Figure 1 shows the major functional units within the MPC8560.

DDR SDRAM

GPIO 32b

IRQs

MPHY UTOPIAs

MIIs, RMIIs

TDMs

I/Os

Serial Interfaces TC - Layer

Time Slot Assigner Time Slot Assigner

DDR SDRAM Controller I2C Controller

Local Bus Controller

Programmable Interrupt Controller

MCC FCC SCC

SPI I2C

Serial DMA

I-Memory

DPRAM

RISC Engine Parallel I/O Baud Rate Generators Timers CPM Interrupt Controller
e500 Coherency

Module
256KB L2-Cache/

SRAM
e500 Core
32 KB L1 I Cache
32 KB L1 D Cache

Core Complex Bus

OCeaN

RapidIO Controller PCI Controller DMA Controller

RapidIO-8 16 Gb/s

PCI 64b 133 MHz
10/100/1000 MAC 10/100/1000 MAC

MII, GMII, TBI, RTBI, RGMIIs

Figure MPC8560 Block Diagram
transactions Sleep mode support for self refresh SDRAM Supports auto refreshing On-the-fly power management using CKE signal Registered DIMM support Fast memory access via JTAG port 2.5-V SSTL2 compatible I/O
• RapidIO interface unit 8-bit RapidIO I/O and messaging protocols Source-synchronous double data rate DDR interfaces Supports small type systems small domain, 8-bit device ID Supports four priority levels ordering within a level Reordering across priority levels Maximum data payload of 256 bytes per packet pacing support at the physical layer CRC protection for packets Supports atomic operations increment, decrement, set, and clear LVDS signaling
• message unit One inbound data message structure inbox One outbound data message structure outbox Supports chaining and direct modes in the outbox Support of up to 16 packets per message Support of up to 256 bytes per packet and up to 4 Kbytes of data per message Supports one inbound doorbell message structure
• Programmable interrupt controller PIC Programming model is compliant with the OpenPIC architecture Supports 16 programmable interrupt and processor task priority levels Supports 12 discrete external interrupts Supports 4 message interrupts with 32-bit messages Supports connection of an external interrupt controller such as the 8259 programmable
interrupt controller Four global high resolution timers/counters that can generate interrupts Supports 22 other internal interrupt sources Supports fully nested interrupt delivery Interrupts can be routed to external pin for external processing

Freescale Semiconductor

Overview

Interrupts can be routed to the e500 core’s standard or critical interrupt inputs Interrupt summary registers allow fast identification of interrupt source
• I2C controller Two-wire interface Multiple master support Master or slave I2C mode support On-chip digital filtering rejects spikes on the bus
• Boot sequencer Optionally loads configuration data from serial ROM at reset via the I2C interface Can be used to initialize configuration registers and/or memory Supports extended I2C addressing mode Data integrity checked with preamble signature and CRC
• Local bus controller LBC Multiplexed 32-bit address and data operating at up to 166 MHz Eight chip selects support eight external slaves Up to eight-beat burst transfers The 32-, 16-, and 8-bit port sizes are controlled by an on-chip memory controller Three protocol engines available on a per chip select basis:

General purpose chip select machine GPCM Three user programmable machines UPMs Dedicated single data rate SDRAM controller Parity support Default boot ROM chip select with configurable bus width 8-,16-, or 32-bit
• Two three-speed 10/100/1Gb Ethernet controllers TSECs Dual IEEE 802.3u, 802.3x, 802.3z, 802.3ac, 802.3ab compliant controllers Support for different Ethernet physical interfaces 10/100/1Gb Mbps IEEE GMII 10/100 Mbps IEEE MII 10 Mbps IEEE MII 1000 Mbps IEEE 802.3z TBI 10/100/1Gb Mbps RGMII/RTBI Full- and half-duplex support Buffer descriptors are backward compatible with MPC8260 and MPC860T 10/100 programming models 9.6-Kbyte jumbo frame support RMON statistics support 2-Kbyte internal transmit and receive FIFOs

Freescale Semiconductor

Overview

MII management interface for control and status Programmable CRC generation and checking Ability to force allocation of header information and buffer descriptors into L2 cache.
• OCeaN switch fabric Four-port crossbar packet switch Reorders packets from a source based on priorities Reorders packets to bypass blocked packets Implements starvation avoidance algorithms Supports packets with payloads of up to 256 bytes
• Integrated DMA controller Four-channel controller All channels accessible by both the local and remote masters Extended DMA functions advanced chaining and striding capability Support for scatter and gather transfers Misaligned transfer capability Interrupt on completed segment, link, list, and error Supports transfers to or from any local memory or I/O port Selectable hardware-enforced coherency snoop/no-snoop Ability to start and flow control each DMA channel from external 3-pin interface Ability to launch DMA from single write transaction
• PCI/PCI-X controller PCI and PCI-X compatible 64- or 32-bit PCI port supports at 16 to 66 MHz 64-bit PCI-X support up to 133 MHz Host and agent mode support 64-bit dual address cycle DAC support PCI-X supports multiple split transactions Supports PCI-to-memory and memory-to-PCI streaming Memory prefetching of PCI read accesses Supports posting of processor-to-PCI and PCI-to-memory writes PCI 3.3-V compatible Selectable hardware-enforced coherency
• Power management Fully static 1.2-V CMOS design with and 2.5-V I/O Supports power saving modes doze, nap, and sleep Employs dynamic power management, which automatically minimizes power consumption of
blocks when they are idle.

Freescale Semiconductor

Electrical Characteristics
• System performance monitor Supports eight 32-bit counters that count the occurrence of selected events Ability to count up to 512 counter-specific events Supports 64 reference events that can be counted on any of the 8 counters Supports duration and quantity threshold counting Burstiness feature that permits counting of burst events with a programmable time between bursts Triggering and chaining capability Ability to generate an interrupt on overflow
• System access port Uses JTAG interface and a TAP controller to access entire system memory map Supports 32-bit accesses to configuration registers Supports cache-line burst accesses to main memory Supports large block 4-Kbyte uploads and downloads Supports continuous bit streaming of entire block for fast upload and download
• IEEE Std 1149.1 -compliant, JTAG boundary scan
• 783 FC-PBGA package
2 Electrical Characteristics

This section provides the electrical specifications and thermal characteristics for the MPC8560. The MPC8560 is currently targeted to these specifications. Some of these specifications are independent of the I/O cell, but are included for a more complete reference. These are not purely I/O buffer design specifications.

Overall DC Electrical Characteristics

This section covers the ratings, conditions, and other characteristics.

Absolute Maximum Ratings

Table 1 provides the absolute maximum ratings.

Table Absolute Maximum Ratings 1

Core supply voltage PLL supply voltage

Characteristic

For devices rated at 667 and 833 MHz For devices rated at 1 GHz

For devices rated at 667 and 833 MHz For devices rated at 1 GHz

Symbol VDD

AVDD

Max Value

Unit Notes

Freescale Semiconductor

Electrical Characteristics

Table Absolute Maximum Ratings 1 continued

Characteristic

Max Value

Unit Notes

DDR DRAM I/O voltage Three-speed Ethernet I/O voltage

GVDD LVDD

CPM, PCI/PCI-X, local bus, RapidIO, 10/100 Ethernet,MII
management, DUART, system control and power management, I2C, and JTAG I/O voltage

OVDD
Items on the same line have no ordering requirement with respect to one another. Items on separate lines must be ordered sequentially such that voltage rails on a previous step must reach 90 percent of their value before the voltage rails on the current step reach 10 percent of theirs.

Freescale Semiconductor

Electrical Characteristics

NOTE

If the items on line 2 must precede items on line 1, please ensure that the delay will not exceed 500 ms and the power sequence is not done greater than once per day in production environment.

NOTE

From a system standpoint, if the I/O power supplies ramp prior to the VDD core supply, the I/Os on the MPC8560 may drive a logic one or zero during power-up.

Recommended Operating Conditions

Table 2 provides the recommended operating conditions for the MPC8560. Note that the values in Table 2 are the recommended and tested operating conditions. Proper device operation outside of these conditions is not guaranteed.

Table Recommended Operating Conditions

Characteristic

Core supply voltage

PLL supply voltage

DDR DRAM I/O voltage Three-speed Ethernet I/O voltage

For devices rated at 667 and 833 MHz For devices rated at 1 GHz

For devices rated at 667 and 833 MHz For devices rated at 1 GHz

AVDD

GVDD LVDD

CPM, PCI/PCI-X, local bus, RapidIO, 10/100 Ethernet, MII management, DUART, system control and power management, I2C, and JTAG I/O voltage

Input voltage

DDR DRAM signals

DDR DRAM reference

Three-speed Ethernet signals

CPM, PCI/PCI-X, local bus, RapidIO, 10/100 Ethernet, MII management, DUART, SYSCLK, system control and power management, I2C, and JTAG signals

Die-junction temperature

OVDD MVIN MVREF LVIN OVIN

Recommended Value

V ± 60 mV V ± 50 mV

V ± 60 mV V ± 50 mV V ± 125 mV V ± 165 mV V ± 125 mV V ± 165 mV

GND to GVDD GND to GVDD/2

GND to LVDD GND to OVDD
0 to 105

Unit V

Freescale Semiconductor

Electrical Characteristics

Figure 2 shows the undershoot and overshoot voltages at the interfaces of the MPC8560.

G/L/OVDD + 20% G/L/OVDD + 5%

G/L/OVDD

GND V VIL

GND V

Not to Exceed 10% of tSYS1
Ordering information for the parts fully covered by this specification document is provided in Section “Part Numbers Fully Addressed by this Document.”

Part Numbers Fully Addressed by this Document

Table Part Numbering Nomenclature
nnnn

Product

Part

Code Identifier

Temperature Range 1

Package 2

Processor

Platform

Frequency 3, 4 Frequency
8560

Blank = 0 to 105°C= -40 to 105°C

PX = FC-PBGA 833 = 833 MHz L = 333 MHz

VT = FC-PBGA 667 = 667 MHz J= 266 MHz Pb-free
8560

Blank = 0 to 105°C = to 105°C

PX = FC-PBGA AQ = GHz VT = FC-PBGA

Pb-free

F = 333 MHz

Notes 1.For Temperature Range=C, Processor Frequency is limited to 667 MHz.
2.See Section 14, “Package and Pin Listings” for more information on available package types.
3.Processor core frequencies supported by parts addressed by this specification only. Not all parts described in this specification support all core frequencies. The core must be clocked at a minimum frequency of 400 MHz. A device must not be used beyond the core frequency or platform frequency indicated on the device.

Designers should use the maximum power value corresponding to the core and platform frequency grades indicated on the device. A lower maximum power value should not be assumed for design purposes even when running at a lower frequency.

Freescale Semiconductor

Part Marking

Parts are marked as the example shown in Figure

Device Nomenclature

MPC8n5nnntppfffcr xAPTXWxLxYxYnWWA

AMTMWMLMYYMWCWCACCC CYWCCWCLCAZ

FC-PBGA
is the 5-digit mask number.

ATWLYYWWA is the traceability code.
is the country of assembly. This space is left blank if parts are assembled in the United States. YWWLAZ is the assembly traceability code.

Figure Part Marking for FC-PBGA Device

Freescale Semiconductor

Device Nomenclature

THIS PAGE INTENTIONALLY LEFT BLANK

Freescale Semiconductor

THIS PAGE INTENTIONALLY LEFT BLANK

More datasheets: 02982001Z | MV5D164 | MV5C164 | MV5A164 | MV5E164 | MV5B164 | KMPC8560VT667LC | KMPC8560VT667LB | KMPC8560CPX667JB | KMPC8560CVT667JB

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Datasheet ID: KMPC8560PX667LB 635553