KMPC8540VT833LB

KMPC8540VT833LB Datasheet

Part	Datasheet
KMPC8540VT833LB	KMPC8540VT833LB (pdf)

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KMPC8540PX667LB	KMPC8540PX667LB
KMPC8540VTAQFB	KMPC8540VTAQFB
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KMPC8540CPX667JB	KMPC8540CPX667JB
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KMPC8540VT667LC	KMPC8540VT667LC
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Freescale Semiconductor Technical Data MPC8540 Integrated Processor Hardware Specifications The MPC8540 integrates a PowerPC processor core built on Power Architecture technology with system logic required for networking, telecommunications, and wireless infrastructure applications. The MPC8540 is a member of the PowerQUICC III family of devices that combine system-level support for industry-standard interfaces with processors that implement the embedded category of the Power Architecture technology. For functional characteristics of the processor, refer to the MPC8540 PowerQUICC III Integrated Host Processor Reference Manual. To locate any published errata or updates for this document, contact your Freescale sales office. Freescale Semiconductor, Inc., All rights reserved. Overview The following section provides a high-level overview of the MPC8540 features. Figure 1 shows the major functional units within the MPC8540. DDR SDRAM ROM, SDRAM, GPIO IRQs DDR SDRAM Controller Local Bus Controller Programmable Interrupt Controller e500 Coherency Module 256KB L2-Cache/ SRAM e500 Core 32 KB L1 I Cache 32 KB L1 D Cache Core Complex Bus MII Serial 10/100 ENET DUART I2C Controller OCeaN RapidIO Controller PCI/PCI-X Controller 4ch DMA Controller RapidIO-8 16 Gb/s PCI-X 64b 133 MHz TSEC 10/100/1G MII, GMII,TBI, RTBI, RGMII TSEC 10/100/1G MII, GMII,TBI, RTBI, RGMII Figure MPC8540 Block Diagram Key Features The following lists an overview of the MPC8540 feature set. • High-performance, 32-bit Book core that implements the Power Architecture 32-Kbyte L1 instruction cache and 32-Kbyte L1 data cache with parity protection. Caches can be locked entirely or on a per-line basis. Separate locking for instructions and data Memory management unit MMU especially designed for embedded applications Enhanced hardware and software debug support Performance monitor facility similar to but different from the MPC8540 performance monitor described in Chapter 18, “Performance Monitor.” Freescale Semiconductor Overview • 256 Kbyte L2 cache/SRAM Can be configured as follows Full cache mode 256-Kbyte cache . Full memory-mapped SRAM mode 256-Kbyte SRAM mapped as a single 256-Kbyte block or two 128-Kbyte blocks Half SRAM and half cache mode 128-Kbyte cache and 128-Kbyte memory-mapped SRAM Full ECC support on 64-bit boundary in both cache and SRAM modes Cache mode supports instruction caching, data caching, or both External masters can force data to be allocated into the cache through programmed memory ranges or special transaction types stashing Eight-way set-associative cache organization 1024 sets of 32-byte cache lines Supports locking the entire cache or selected lines. Individual line locks are set and cleared through Book E instructions or by externally mastered transactions Global locking and flash clearing done through writes to L2 configuration registers Instruction and data locks can be flash cleared separately Read and write buffering for internal bus accesses SRAM features include the following I/O devices access SRAM regions by marking transactions as snoopable global Regions can reside at any aligned location in the memory map Byte accessible ECC is protected using read-modify-write transactions accesses for smaller than cache-line accesses. Sleep mode support for self refresh SDRAM Supports auto refreshing On-the-fly power management using CKE signal Registered DIMM support Fast memory access via JTAG port 2.5-V SSTL2 compatible I/O • RapidIO interface unit 8-bit RapidIO I/O and messaging protocols Source-synchronous double data rate DDR interfaces Supports small type systems small domain, 8-bit device ID Supports four priority levels ordering within a level Reordering across priority levels Maximum data payload of 256 bytes per packet pacing support at the physical layer CRC protection for packets Supports atomic operations increment, decrement, set, and clear LVDS signaling • message unit One inbound data message structure inbox One outbound data message structure outbox Supports chaining and direct modes in the outbox Support of up to 16 packets per message Support of up to 256 bytes per packet and up to 4 Kbytes of data per message Supports one inbound doorbell message structure • Programmable interrupt controller PIC Programming model is compliant with the OpenPIC architecture Supports 16 programmable interrupt and processor task priority levels Supports 12 discrete external interrupts Supports 4 message interrupts with 32-bit messages Supports connection of an external interrupt controller such as the 8259 programmable interrupt controller Four global high resolution timers/counters that can generate interrupts Supports 22 other internal interrupt sources Supports fully nested interrupt delivery Interrupts can be routed to external pin for external processing Freescale Semiconductor Overview Interrupts can be routed to the e500 core’s standard or critical interrupt inputs Interrupt summary registers allow fast identification of interrupt source • I2C controller Two-wire interface Multiple master support Master or slave I2C mode support On-chip digital filtering rejects spikes on the bus • Boot sequencer Optionally loads configuration data from serial ROM at reset via the I2C interface Can be used to initialize configuration registers and/or memory Supports extended I2C addressing mode Data integrity checked with preamble signature and CRC • DUART Two 4-wire interfaces SIN, SOUT, RTS, CTS Programming model compatible with the original 16450 UART and the PC16550D • 10/100 fast Ethernet controller FEC Operates at 10 to 100 megabits per second Mbps as a device debug and maintenance port • Local bus controller LBC Multiplexed 32-bit address and data operating at up to 166 MHz Eight chip selects support eight external slaves Up to eight-beat burst transfers The 32-, 16-, and 8-bit port sizes are controlled by an on-chip memory controller Three protocol engines available on a per chip select basis: General purpose chip select machine GPCM Three user programmable machines UPMs Dedicated single data rate SDRAM controller Parity support Default boot ROM chip select with configurable bus width 8-,16-, or 32-bit • Two three-speed 10/100/1Gb Ethernet controllers TSECs Dual IEEE 802.3u, 802.3x, 802.3z, 802.3ac, 802.3ab compliant controllers Support for different Ethernet physical interfaces 10/100/1Gb Mbps IEEE GMII 10/100 Mbps IEEE MII 10 Mbps IEEE MII 1000 Mbps IEEE 802.3z TBI 10/100/1Gb Mbps RGMII/RTBI Full- and half-duplex support Freescale Semiconductor Overview Buffer descriptors are backward compatible with MPC8260 and MPC860T 10/100 programming models 9.6-Kbyte jumbo frame support RMON statistics support 2-Kbyte internal transmit and receive FIFOs MII management interface for control and status Programmable CRC generation and checking Ability to force allocation of header information and buffer descriptors into L2 cache. • OCeaN switch fabric Four-port crossbar packet switch Reorders packets from a source based on priorities Reorders packets to bypass blocked packets Implements starvation avoidance algorithms Supports packets with payloads of up to 256 bytes • Integrated DMA controller Four-channel controller All channels accessible by both the local and remote masters Extended DMA functions advanced chaining and striding capability Support for scatter and gather transfers Misaligned transfer capability Interrupt on completed segment, link, list, and error Supports transfers to or from any local memory or I/O port Selectable hardware-enforced coherency snoop/no-snoop Ability to start and flow control each DMA channel from external 3-pin interface Ability to launch DMA from single write transaction • PCI/PCI-X controller PCI and PCI-X compatible 64- or 32-bit PCI port supports at 16 to 66 MHz 64-bit PCI-X support up to 133 MHz Host and agent mode support 64-bit dual address cycle DAC support PCI-X supports multiple split transactions Supports PCI-to-memory and memory-to-PCI streaming Memory prefetching of PCI read accesses Supports posting of processor-to-PCI and PCI-to-memory writes PCI 3.3-V compatible Selectable hardware-enforced coherency Freescale Semiconductor Electrical Characteristics • Power management Fully static 1.2-V CMOS design with and 2.5-V I/O Supports power saving modes doze, nap, and sleep Employs dynamic power management, which automatically minimizes power consumption of blocks when they are idle. • System performance monitor Supports eight 32-bit counters that count the occurrence of selected events Ability to count up to 512 counter-specific events Supports 64 reference events that can be counted on any of the 8 counters Supports duration and quantity threshold counting Burstiness feature that permits counting of burst events with a programmable time between bursts Triggering and chaining capability Ability to generate an interrupt on overflow • System access port Uses JTAG interface and a TAP controller to access entire system memory map Supports 32-bit accesses to configuration registers Supports cache-line burst accesses to main memory Supports large block 4-Kbyte uploads and downloads Supports continuous bit streaming of entire block for fast upload and download • IEEE 1149.1-compliant, JTAG boundary scan • 783 FC-PBGA package 2 Electrical Characteristics This section provides the electrical specifications and thermal characteristics for the MPC8540. The MPC8540 is currently targeted to these specifications. Some of these specifications are independent of the I/O cell, but are included for a more complete reference. These are not purely I/O buffer design specifications. Freescale Semiconductor Electrical Characteristics Overall DC Electrical Characteristics This section covers the ratings, conditions, and other characteristics. Absolute Maximum Ratings Table 1 provides the absolute maximum ratings. Table Absolute Maximum Ratings 1 Characteristic Max Value Unit Notes Core supply voltage VDD For devices rated at 667 and 833 MHz For devices rated at 1 GHz PLL supply voltage AVDD For devices rated at 667 and 833 MHz For devices rated at 1 GHz DDR DRAM I/O voltage Three-speed Ethernet I/O voltage GVDD LVDD PCI/PCI-X, local bus, RapidIO, 10/100 Ethernet, MII management, DUART, system control and power management, I2C, and JTAG I/O voltage OVDD VDD, AVDD GVDD, LVDD, OVDD I/O supplies Items on the same line have no ordering requirement with respect to one another. Items on separate lines must be ordered sequentially such that voltage rails on a previous step must reach 90 percent of their value before the voltage rails on the current step reach 10 percent of theirs. NOTE If the items on line 2 must precede items on line 1, please ensure that the delay will not exceed 500 ms and the power sequence is not done greater than once per day in production environment. NOTE From a system standpoint, if the I/O power supplies ramp prior to the VDD core supply, the I/Os on the MPC8540 may drive a logic one or zero during power-up. Recommended Operating Conditions Table 2 provides the recommended operating conditions for the MPC8540. Note that the values in Table 2 are the recommended and tested operating conditions. Proper device operation outside of these conditions is not guaranteed. Table Recommended Operating Conditions Characteristic Recommended Value Unit Core supply voltage VDD For devices rated at 667 and 833 MHz For devices rated at 1 GHz V ± 60 mV V ± 50 mV PLL supply voltage AVDD For devices rated at 667 and 833 MHz V ± 60 mV For devices rated at 1 GHz V ± 50 mV DDR DRAM I/O voltage Three-speed Ethernet I/O voltage GVDD V ± 125 mV LVDD V ± 165 mV V ± 125 mV PCI/PCI-X, local bus, RapidIO, 10/100 Ethernet, MII management, DUART, system control and power management, I2C, and JTAG I/O voltage OVDD V ± 165 mV Freescale Semiconductor Electrical Characteristics Table Recommended Operating Conditions continued Input voltage Die-junction temperature Characteristic DDR DRAM signals DDR DRAM reference Three-speed Ethernet signals PCI/PCI-X, local bus, RapidIO, 10/100 Ethernet, MII management, DUART, SYSCLK, system control and power management, I2C, and JTAG signals MVIN MVREF LVIN OVIN Ordering information for the parts fully covered by this specification document is provided in Section “Nomenclature of Parts Fully Addressed by this Document.” Nomenclature of Parts Fully Addressed by this Document Table Part Numbering Nomenclature nnnn Product Part Code Identifier Temperature Range1 Package 2 Processor Platform Frequency 3, 4 Frequency 8540 Blank = 0 to 105°C = to 105°C Blank = 0 to 105°C = to 105°C PX = FC-PBGA 833 = 833 MHz VT = FC-PBGA 667 = 667 MHz Pb-free PX = FC-PBGA AQ = GHz VT = FC-PBGA Pb-free L = 333 MHz J = 266 MHz F = 333 MHz 1.For Temperature Range=C, Processor Frequency is limited to 667 MHz. 2.See Section 14, “Package and Pin Listings,” for more information on available package types. 3.Processor core frequencies supported by parts addressed by this specification only. Not all parts described in this specification support all core frequencies. The core must be clocked at a minimum frequency of 400MHz. A device must not be used beyond the core frequency or platform frequency indicated on the device. 4.Designers should use the maximum power value corresponding to the core and platform frequency grades indicated on the device. A lower maximum power value should not be assumed for design purposes even when running at a lower frequency. Freescale Semiconductor Part Marking Parts are marked as the example shown in Figure Device Nomenclature MPCn8n5nntppfffcr xAPTXWxLxYxYnWWA AMTMWMLMYYMWCWCACCC CYWCCWCLCAZ 85xx FC-PBGA is the 5-digit mask number. ATWLYYWWA is the traceability code. is the country of assembly. This space is left blank if parts are assembled in the United States. YWWLAZ is the assembly traceability code. Figure Part Marking for FC-PBGA Device Freescale Semiconductor Device Nomenclature THIS PAGE INTENTIONALLY LEFT BLANK Freescale Semiconductor THIS PAGE INTENTIONALLY LEFT BLANK Device Nomenclature

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Freescale Semiconductor

Technical Data

MPC8540 Integrated Processor Hardware Specifications

The MPC8540 integrates a PowerPC processor core built on Power Architecture technology with system logic required for networking, telecommunications, and wireless infrastructure applications. The MPC8540 is a member of the PowerQUICC III family of devices that combine system-level support for industry-standard interfaces with processors that implement the embedded category of the Power Architecture technology. For functional characteristics of the processor, refer to the MPC8540 PowerQUICC III Integrated Host Processor Reference Manual.

To locate any published errata or updates for this document, contact your Freescale sales office.

Freescale Semiconductor, Inc., All rights reserved.

Overview

The following section provides a high-level overview of the MPC8540 features. Figure 1 shows the major functional units within the MPC8540.

DDR SDRAM

ROM, SDRAM,

GPIO

IRQs

DDR SDRAM Controller

Local Bus Controller

Programmable Interrupt Controller
e500 Coherency

Module
256KB L2-Cache/

SRAM
e500 Core
32 KB L1 I Cache
32 KB L1 D Cache

Core Complex Bus

MII Serial
10/100 ENET

DUART

I2C Controller

OCeaN

RapidIO Controller PCI/PCI-X Controller 4ch DMA Controller

RapidIO-8 16 Gb/s

PCI-X 64b 133 MHz

TSEC 10/100/1G

MII, GMII,TBI, RTBI, RGMII

TSEC 10/100/1G

MII, GMII,TBI, RTBI, RGMII

Figure MPC8540 Block Diagram

Key Features

The following lists an overview of the MPC8540 feature set.
• High-performance, 32-bit Book core that implements the Power Architecture 32-Kbyte L1 instruction cache and 32-Kbyte L1 data cache with parity protection. Caches can be locked entirely or on a per-line basis. Separate locking for instructions and data Memory management unit MMU especially designed for embedded applications Enhanced hardware and software debug support Performance monitor facility similar to but different from the MPC8540 performance monitor described in Chapter 18, “Performance Monitor.”

Freescale Semiconductor

Overview
• 256 Kbyte L2 cache/SRAM Can be configured as follows Full cache mode 256-Kbyte cache . Full memory-mapped SRAM mode 256-Kbyte SRAM mapped as a single 256-Kbyte block or two 128-Kbyte blocks Half SRAM and half cache mode 128-Kbyte cache and 128-Kbyte memory-mapped SRAM Full ECC support on 64-bit boundary in both cache and SRAM modes Cache mode supports instruction caching, data caching, or both External masters can force data to be allocated into the cache through programmed memory ranges or special transaction types stashing Eight-way set-associative cache organization 1024 sets of 32-byte cache lines Supports locking the entire cache or selected lines. Individual line locks are set and cleared through Book E instructions or by externally mastered transactions Global locking and flash clearing done through writes to L2 configuration registers Instruction and data locks can be flash cleared separately Read and write buffering for internal bus accesses SRAM features include the following I/O devices access SRAM regions by marking transactions as snoopable global Regions can reside at any aligned location in the memory map Byte accessible ECC is protected using read-modify-write transactions accesses for smaller than cache-line accesses.
Sleep mode support for self refresh SDRAM Supports auto refreshing On-the-fly power management using CKE signal Registered DIMM support Fast memory access via JTAG port 2.5-V SSTL2 compatible I/O
• RapidIO interface unit 8-bit RapidIO I/O and messaging protocols Source-synchronous double data rate DDR interfaces Supports small type systems small domain, 8-bit device ID Supports four priority levels ordering within a level Reordering across priority levels Maximum data payload of 256 bytes per packet pacing support at the physical layer CRC protection for packets Supports atomic operations increment, decrement, set, and clear LVDS signaling
• message unit One inbound data message structure inbox One outbound data message structure outbox Supports chaining and direct modes in the outbox Support of up to 16 packets per message Support of up to 256 bytes per packet and up to 4 Kbytes of data per message Supports one inbound doorbell message structure
• Programmable interrupt controller PIC Programming model is compliant with the OpenPIC architecture Supports 16 programmable interrupt and processor task priority levels Supports 12 discrete external interrupts Supports 4 message interrupts with 32-bit messages Supports connection of an external interrupt controller such as the 8259 programmable
interrupt controller Four global high resolution timers/counters that can generate interrupts Supports 22 other internal interrupt sources Supports fully nested interrupt delivery Interrupts can be routed to external pin for external processing

Freescale Semiconductor

Overview

Interrupts can be routed to the e500 core’s standard or critical interrupt inputs Interrupt summary registers allow fast identification of interrupt source
• I2C controller Two-wire interface Multiple master support Master or slave I2C mode support On-chip digital filtering rejects spikes on the bus
• Boot sequencer Optionally loads configuration data from serial ROM at reset via the I2C interface Can be used to initialize configuration registers and/or memory Supports extended I2C addressing mode Data integrity checked with preamble signature and CRC
• DUART Two 4-wire interfaces SIN, SOUT, RTS, CTS Programming model compatible with the original 16450 UART and the PC16550D
• 10/100 fast Ethernet controller FEC Operates at 10 to 100 megabits per second Mbps as a device debug and maintenance port
• Local bus controller LBC Multiplexed 32-bit address and data operating at up to 166 MHz Eight chip selects support eight external slaves Up to eight-beat burst transfers The 32-, 16-, and 8-bit port sizes are controlled by an on-chip memory controller Three protocol engines available on a per chip select basis:

General purpose chip select machine GPCM Three user programmable machines UPMs Dedicated single data rate SDRAM controller Parity support Default boot ROM chip select with configurable bus width 8-,16-, or 32-bit
• Two three-speed 10/100/1Gb Ethernet controllers TSECs Dual IEEE 802.3u, 802.3x, 802.3z, 802.3ac, 802.3ab compliant controllers Support for different Ethernet physical interfaces 10/100/1Gb Mbps IEEE GMII 10/100 Mbps IEEE MII 10 Mbps IEEE MII 1000 Mbps IEEE 802.3z TBI 10/100/1Gb Mbps RGMII/RTBI Full- and half-duplex support

Freescale Semiconductor

Overview

Buffer descriptors are backward compatible with MPC8260 and MPC860T 10/100 programming models
9.6-Kbyte jumbo frame support RMON statistics support 2-Kbyte internal transmit and receive FIFOs MII management interface for control and status Programmable CRC generation and checking Ability to force allocation of header information and buffer descriptors into L2 cache.
• OCeaN switch fabric Four-port crossbar packet switch Reorders packets from a source based on priorities Reorders packets to bypass blocked packets Implements starvation avoidance algorithms Supports packets with payloads of up to 256 bytes
• Integrated DMA controller Four-channel controller All channels accessible by both the local and remote masters Extended DMA functions advanced chaining and striding capability Support for scatter and gather transfers Misaligned transfer capability Interrupt on completed segment, link, list, and error Supports transfers to or from any local memory or I/O port Selectable hardware-enforced coherency snoop/no-snoop Ability to start and flow control each DMA channel from external 3-pin interface Ability to launch DMA from single write transaction
• PCI/PCI-X controller PCI and PCI-X compatible 64- or 32-bit PCI port supports at 16 to 66 MHz 64-bit PCI-X support up to 133 MHz Host and agent mode support 64-bit dual address cycle DAC support PCI-X supports multiple split transactions Supports PCI-to-memory and memory-to-PCI streaming Memory prefetching of PCI read accesses Supports posting of processor-to-PCI and PCI-to-memory writes PCI 3.3-V compatible Selectable hardware-enforced coherency

Freescale Semiconductor

Electrical Characteristics
• Power management Fully static 1.2-V CMOS design with and 2.5-V I/O Supports power saving modes doze, nap, and sleep Employs dynamic power management, which automatically minimizes power consumption of blocks when they are idle.
• System performance monitor Supports eight 32-bit counters that count the occurrence of selected events Ability to count up to 512 counter-specific events Supports 64 reference events that can be counted on any of the 8 counters Supports duration and quantity threshold counting Burstiness feature that permits counting of burst events with a programmable time between bursts Triggering and chaining capability Ability to generate an interrupt on overflow
• System access port Uses JTAG interface and a TAP controller to access entire system memory map Supports 32-bit accesses to configuration registers Supports cache-line burst accesses to main memory Supports large block 4-Kbyte uploads and downloads Supports continuous bit streaming of entire block for fast upload and download
• IEEE 1149.1-compliant, JTAG boundary scan
• 783 FC-PBGA package
2 Electrical Characteristics

This section provides the electrical specifications and thermal characteristics for the MPC8540. The MPC8540 is currently targeted to these specifications. Some of these specifications are independent of the I/O cell, but are included for a more complete reference. These are not purely I/O buffer design specifications.

Freescale Semiconductor

Electrical Characteristics

Overall DC Electrical Characteristics

This section covers the ratings, conditions, and other characteristics.

Absolute Maximum Ratings

Table 1 provides the absolute maximum ratings.

Table Absolute Maximum Ratings 1

Characteristic

Max Value

Unit Notes

Core supply voltage

VDD For devices rated at 667 and 833 MHz

For devices rated at 1 GHz

PLL supply voltage

AVDD

For devices rated at 667 and 833 MHz

For devices rated at 1 GHz

DDR DRAM I/O voltage Three-speed Ethernet I/O voltage

GVDD

LVDD

PCI/PCI-X, local bus, RapidIO, 10/100 Ethernet, MII management, DUART, system control and power management, I2C, and JTAG

I/O voltage

OVDD
VDD, AVDD GVDD, LVDD, OVDD I/O supplies Items on the same line have no ordering requirement with respect to one another. Items on separate lines must be ordered sequentially such that voltage rails on a previous step must reach 90 percent of their value before the voltage rails on the current step reach 10 percent of theirs.

NOTE

If the items on line 2 must precede items on line 1, please ensure that the delay will not exceed 500 ms and the power sequence is not done greater than once per day in production environment.

NOTE

From a system standpoint, if the I/O power supplies ramp prior to the VDD core supply, the I/Os on the MPC8540 may drive a logic one or zero during power-up.

Recommended Operating Conditions

Table 2 provides the recommended operating conditions for the MPC8540. Note that the values in Table 2 are the recommended and tested operating conditions. Proper device operation outside of these conditions is not guaranteed.

Table Recommended Operating Conditions

Characteristic

Recommended Value

Unit

Core supply voltage

VDD For devices rated at 667 and 833 MHz

For devices rated at 1 GHz

V ± 60 mV V ± 50 mV

PLL supply voltage

AVDD

For devices rated at 667 and 833 MHz

V ± 60 mV

For devices rated at 1 GHz

V ± 50 mV

DDR DRAM I/O voltage Three-speed Ethernet I/O voltage

GVDD

V ± 125 mV

LVDD

V ± 165 mV

V ± 125 mV

PCI/PCI-X, local bus, RapidIO, 10/100 Ethernet, MII management, DUART, system control and power management, I2C, and JTAG I/O voltage

OVDD

V ± 165 mV

Freescale Semiconductor

Electrical Characteristics

Table Recommended Operating Conditions continued

Input voltage Die-junction temperature

Characteristic

DDR DRAM signals

DDR DRAM reference

Three-speed Ethernet signals

PCI/PCI-X, local bus, RapidIO, 10/100 Ethernet, MII management, DUART, SYSCLK, system control and power management, I2C, and JTAG signals

MVIN MVREF

LVIN OVIN
Ordering information for the parts fully covered by this specification document is provided in Section “Nomenclature of Parts Fully Addressed by this Document.”

Nomenclature of Parts Fully Addressed by this Document

Table Part Numbering Nomenclature
nnnn

Product Part Code Identifier

Temperature Range1

Package 2

Processor

Platform

Frequency 3, 4 Frequency
8540

Blank = 0 to 105°C = to 105°C

Blank = 0 to 105°C = to 105°C

PX = FC-PBGA 833 = 833 MHz VT = FC-PBGA 667 = 667 MHz

Pb-free

PX = FC-PBGA AQ = GHz VT = FC-PBGA

Pb-free

L = 333 MHz J = 266 MHz

F = 333 MHz
1.For Temperature Range=C, Processor Frequency is limited to 667 MHz.
2.See Section 14, “Package and Pin Listings,” for more information on available package types.
3.Processor core frequencies supported by parts addressed by this specification only. Not all parts described in this specification support all core frequencies. The core must be clocked at a minimum frequency of 400MHz. A device must not be used beyond the core frequency or platform frequency indicated on the device.
4.Designers should use the maximum power value corresponding to the core and platform frequency grades indicated on the device. A lower maximum power value should not be assumed for design purposes even when running at a lower frequency.

Freescale Semiconductor

Part Marking

Parts are marked as the example shown in Figure

Device Nomenclature

MPCn8n5nntppfffcr xAPTXWxLxYxYnWWA

AMTMWMLMYYMWCWCACCC CYWCCWCLCAZ
85xx

FC-PBGA
is the 5-digit mask number.

ATWLYYWWA is the traceability code.
is the country of assembly. This space is left blank if parts are assembled in the United States. YWWLAZ is the assembly traceability code.

Figure Part Marking for FC-PBGA Device

Freescale Semiconductor

Device Nomenclature

THIS PAGE INTENTIONALLY LEFT BLANK

Freescale Semiconductor

THIS PAGE INTENTIONALLY LEFT BLANK

Device Nomenclature

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Datasheet ID: KMPC8540VT833LB 635552