Document Number MPC8347EEC Rev. 11, 02/2009
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MPC8347EVRAGD (pdf) |
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MPC8347EVVAGD |
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KMPC8347CVRAGDB |
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KMPC8347CZUAJDB |
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MPC8347ECZUAGDB |
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MPC8347VRADDB |
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MPC8347ECVRAGDB |
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MPC8347CVRAGDB |
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MPC8347VVAJDB |
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MPC8347ZUAJDB |
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MPC8347EZQAGDB |
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MPC8347ECZQAGDB |
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MPC8347EVRAGDB |
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MPC8347CZUAGDB |
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MPC8347ECZQADDB |
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MPC8347ECVRADDB |
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MPC8347EVVAGDB |
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MPC8347ZUAGDB |
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PDF Datasheet Preview |
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Freescale Semiconductor Technical Data MPC8347E PowerQUICC II Pro Integrated Host Processor Hardware Specifications The MPC8347E PowerQUICC II Pro is a next generation PowerQUICC II integrated host processor. The MPC8347E contains a PowerPC processor core built on Power Architecture technology with system logic for networking, storage, and general-purpose embedded applications. For functional characteristics of the processor, refer to the MPC8349E PowerQUICC II Pro Integrated Host Processor Family Reference Manual. To locate published errata or updates for this document, refer to the MPC8347E product summary page on our website listed on the back cover of this document or, contact your local Freescale sales office. NOTE Freescale Semiconductor, Inc., All rights reserved. Overview This section provides a high-level overview of the MPC8347E features. Figure 1 shows the major functional units within the MPC8347E. Security DUART Dual I2C Timers GPIO e300 Core Interrupt 32KB Controller D-Cache 32KB I-Cache Local Bus DDR SDRAM Controller High-Speed USB 10/100/1000 10/100/1000 Ethernet Ethernet Dual Role Host Figure MPC8347E Block Diagram Major features of the MPC8347E are as follows • Embedded PowerPC e300 processor core operates at up to 667 MHz High-performance, superscalar processor core Floating-point, integer, load/store, system register, and branch processing units 32-Kbyte instruction cache, 32-Kbyte data cache Lockable portion of L1 cache Dynamic power management Software-compatible with the other Freescale processor families that implement Power Architecture technology • Double data rate, DDR SDRAM memory controller Programmable timing for DDR-1 SDRAM 32- or 64-bit data interface, up to 333-MHz data rate for TBGA, 266 MHz for PBGA Four banks of memory, each up to 1 Gbyte DRAM chip configurations from 64 Mbit to 1 Gbit with x8/x16 data ports Full error checking and correction ECC support Page mode support up to 16 simultaneous open pages Contiguous or discontiguous memory mapping Read-modify-write support Sleep mode for self-refresh SDRAM Auto refresh Freescale Semiconductor Overview On-the-fly power management using CKE Registered DIMM support 2.5-V SSTL2 compatible I/O • Dual three-speed 10/100/1000 Ethernet controllers TSECs Dual controllers designed to comply with IEEE standards Ethernet physical interfaces: Freescale Semiconductor Overview Freescale Semiconductor Overview Freescale Semiconductor Overview Data chaining and direct mode Interrupt on completed segment and chain • DUART Two 4-wire interfaces RxD, TxD, RTS, CTS Programming model compatible with the original 16450 UART and the PC16550D • Serial peripheral interface SPI for master or slave • General-purpose parallel I/O GPIO 52 parallel I/O pins multiplexed on various chip interfaces • System timers Periodic interrupt timer Real-time clock Software watchdog timer Eight general-purpose timers • Designed to comply with IEEE Std. JTAG boundary scan • Integrated PCI bus and SDRAM clock generation Freescale Semiconductor Electrical Characteristics 2 Electrical Characteristics This section provides the AC and DC electrical specifications and thermal characteristics for the MPC8347E. The MPC8347E is currently targeted to these specifications. Some of these specifications are independent of the I/O cell, but are included for a more complete reference. These are not purely I/O buffer design specifications. Overall DC Electrical Characteristics This section covers the ratings, conditions, and other characteristics. Absolute Maximum Ratings Table 1 provides the absolute maximum ratings. Table Absolute Maximum Ratings1 In Table 54, “Operating Frequencies for TBGA,” in the ‘Coherent system bus frequency csb_clk ’ row, changed the value in the 533 MHz column to In Table 60, “Suggested PLL Configurations,” under the subhead, ‘33 MHz CLKIN/PCI_CLK Options,’ added row A03 between Ref. No. 724 and Under the subhead ‘66 MHz CLKIN/PCI_CLK Options,’ added row 503 between Ref. No. 305 and For Ref. No. 306, changed the CORE PLL value to In Section 23, “Ordering Information,” replaced first paragraph and added a note. In Section “Part Numbers Fully Addressed by This Document,” replaced first paragraph. Freescale Semiconductor 5 4 3 2 Date 2/2007 8/2006 3/2006 10/2005 9/2005 8/2005 5/2005 Substantive Change s Section 2, “Electrical Characteristics,” moved to second section and all other section, table, and figure numbering change accordingly. Table 7, “CLKIN AC Timing Specifications:” Changed max rise and fall time from to Table 22, “GMII Receive AC Timing Specifications:” Changed min tTTKHDX from to Table 30, “MII Management AC Timing Specifications:” Changed max value of tMDKHDX from 70 to Table 34, “Local Bus General Timing on:” Changed min tLBIVKH2 from to Table 36, “JTAG interface DC Electrical Characteristics:” Changed VIH input high voltage min to Table 54, “Operating Frequencies for TBGA:” • Updated TBD values. • Changed maximum coherent system bus frequency for TBGA 667-MHz device to 333 MHz. Table 55, “Operating Frequencies for PBGA:” • Updated TBD values. • Changed PBGA maximum coherent system bus frequency to 266 MHz, and maximum DDR memory bus frequency to 133 MHz. Table 60, “Suggested PLL Configurations” Removed some values from suggested PLL configurations for reference numbers 902, 922, 903, and Table 67, “Part Numbering Nomenclature” Updated TBD values in note Added Table 68, “SVR Settings.” Added Section “Part Marking.” In Table 57, updated AAVID 30x30x9.4 mm Pin Fin natural convection junction-to-ambient thermal resistance, from 11 to Added Table 2, “MPC8347E Typical I/O Power Dissipation.” Table 1 Typical values for power dissipation are changed to TBD. Table 48 Footnote numbering was wrong. THERM0 should have footnote 9 instead of Freescale Semiconductor Date 4/2005 4/2005 Substantive Change s Table 1 Addition of note 1 Table 48 Addition of Therm0 K32 Table 49 Addition of Therm0 B15 Initial release. Freescale Semiconductor Ordering Information 23 Ordering Information This section presents ordering information for the device discussed in this document, and it shows an example of how the parts are marked. Part Numbers Fully Addressed by This Document Table Part Numbering Nomenclature MPC nnnn Product Part Encryption Code Identifier Acceleration Temperature1 Range Package2 Frequency3 Frequency Level 8347 Blank = Not included E = included Blank = 0 to 105°C = to 105°C ZU =TBGA VV = PB free TBGA ZQ = PBGA VR = PB Free PBGA e300 core speed AD = 266 AG = 400 AJ = 533 AL = 667 D = 266 Blank = F = 3334 Notes For temperature range = C, processor frequency is limited to 400 PBGA with a platform frequency of 266 and up to 667 TBGA with a platform frequency of 333 See Section 18, “Package and Pin Listings,” for more information on available package types. Processor core frequencies supported by parts addressed by this specification only. Not all parts described in this specification support all core frequencies. Additionally, parts addressed by Part Number Specifications may support other maximum core frequencies. ALF marked parts support DDR1 up to 333 MHz at 333 MHz CSB as the 'F' marking implies and DDR2 up to 400 MHz at 200 MHz CSB . AJF marked parts support DDR1 and DDR2 up to 333 MHz at a CSB of 333 MHz , but DDR2 at 400 MHz CSB at 200 MHz is NOT guaranteed. Table 68 shows the SVR settings by device and package type. Table SVR Settings Device MPC8347E MPC8347 Package TBGA Freescale Semiconductor Table SVR Settings continued MPC8347E MPC8347 PBGA 8054_0010 8055_0010 Part Marking Parts are marked as in the example shown in Figure Ordering Information MPCnnnnetppaaar core/platform MHZ ATWLYYWW YWWLAZ TBGA/PBGA ATWLYYWW is the traceability code. is the country code. is the mask number. YWWLAZ is the assembly traceability code. Figure Freescale Part Marking for TBGA or PBGA Devices Freescale Semiconductor Ordering Information THIS PAGE INTENTIONALLY LEFT BLANK Freescale Semiconductor THIS PAGE INTENTIONALLY LEFT BLANK Ordering Information Freescale Semiconductor How to Reach Us: Home Page: Web Support: USA/Europe or Locations Not Listed Freescale Semiconductor, Inc. Technical Information Center, EL516 2100 East Elliot Road Tempe, Arizona 85284 +1-800-521-6274 or +1-480-768-2130 Europe, Middle East, and Africa Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 English +46 8 52200080 English +49 89 92103 559 German +33 1 69 35 48 French Japan Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 Asia/Pacific Freescale Semiconductor Hong Kong Ltd. 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More datasheets: MPC8347EZUAGDB | MPC8347EVVAGD | MPC8347EZUALFB | MPC8347EVRADD | MPC8347EVRADDB | MPC8347CZQADDB | MPC8347VRADD | MPC8347EZQADD | MPC8347VRAGD | MPC8347EVVAJD |
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