MC9S12UF32PU

MC9S12UF32PU Datasheet

MC9S12UF32 System on a Chip Guide

Part	Datasheet
MC9S12UF32PU	MC9S12UF32PU (pdf)

Related Parts	Information
MC9S12UF32PB	MC9S12UF32PB

PDF Datasheet Preview
MC9S12UF32 System on a Chip Guide V01.05 TSPG - 8/16 Bit MCU Design, HKG Freescale Semiconductor, Inc. This product has been designed for use in “Commercial” applications. Please see a description below. Freescale’s semiconductor products are classified into the following three tiers “Commercial”, “Industrial”, and “Automotive”. A product should only be used in applications appropriate to its tier. The recommended applications for products in the different tiers are indicated below. For questions, please contact a Freescale sales representative. Commercial Typically 5 year applications - personal computers, PDA’s, portable telecom products, consumer electronics, etc. Industrial Typically 10 year applications - installed telecom equipment, work stations, servers, etc. These products can also be used for Commercial applications. Automotive Qualified per automotive industry standard methods. Release Number 17JAN02 19FEB02 26APR02 16SEP02 25SEP02 03JUN03 11JUN03 13JUL03 Author Y.H. Cheng Y.H. Cheng Y.H. Cheng Y.H. Cheng Y.H. Cheng Y.H. Cheng Y.H. Cheng Y.H. Cheng Summary of Changes Initial Version Device pinout to separate D+ D- for high speed and low speed operation. Remap Timer pins to Port R. Update BG references. Device pinout per IP requirement Add SCI Update Interrupt information. Change pin location for REF3V and VREGEN minor update on module name references remove references to pseudo stop and clock monitor - Updated info for SMRAM3P5K2E in device memory map - Updated EXTAL and XTAL supply rail information. - Relocate SCI module base address from to - Relocate ATA5HC module base address from to - Relocate PIM module base address from to - Relocate Interrupt Vectors - Updated Phy evaluation pinout. - Updated CFA00, CFA01 and CFA02 pin name to CFA0, CFA1 and CFA2 respectively. - Removed ESD and Latchup section in Electrical. - Update Block Guide References - Miscellaneous Typo mistakes. - Update typo in interrupt vector table for Vector - Update typo in pin order of IOC[7:4] in signal properties table - Specify run and wait IDDs in Electrical Section - Specify stop IDD at room temperature in Electrical Section - Change to include 64 pin option - ROMCTL pin assigned to PJ2 Freescale Semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Freescale Semiconductor does not assume any liability arising out of the application or use of any product or circuit described herein neither does it convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. FreescaleTM and the Freescale logo are registered trademarks of Freescale Semiconductor, Inc. Freescale Semiconductor, Inc. is an Equal Opportunity/Affirmative Action Employer. Freescale Semiconductor, Inc. 2004 Freescale Semiconductor Release Number 21AUG03 28NOV03 23MAR04 20APR04 10MAY04 03DEC04 Author Y.H. Cheng Wai-On Law Y.H. Cheng Wai-On Law Wai-On Law Wai-On Law System on a Chip Guide 9S12UF32DGV1/D V01.05 Summary of Changes - Removed all references to XCLKS, since function is removed. - typo - replaced PRU with RPU. - typo - replaced ATAHC with ATA5HC - Removed references to clock monitor, since function is not available. - Update for 100-pin and 64-pin packages. - Add footnotes on IRQ pin removal in 64-pin package - Update Flash memory map out of reset. - Add information on INITRM, INITRG, INITEE setting for example application memory map - Update clock distribution diagram to make it more intelligible - Change table 2-3, 2-5 description using general purpose port references instead of Functional module references. - Stop IDD spec for -40C and 85C are removed - Add other conditions for RUN Idd and Wait Idd. - Minor typo corrections. - Corrected ‘Background Debug Module’ to ‘HCS12 Breakpoint’ at address in table - Added detailed register map. - Corrected the MSHC enable control in table - Added part ID for mask 1L47S. - Removed all references and description on USB Physical Endpoint 6 - Updated IDD, 3V and 5V I/O electricals and package thermal resistance information - Include Commercial tier note - Update and add note to detailed register map. - Added PIM reference. - Added package information as appendix B. - Improved - Fixed consistency of 3.0v and 3.3v for VDD3X. - Updated power dissipation formula. - Added schematic and PCB layout recommendations. - Added NVM, VREGU, CRGU electricals to appendix A. Figure 0-1 provides an ordering number example. MC9S12 UF32 FU Package Option Device Title Controller Family Package Options PB = 64LQFP PU = 100LQFP Figure 0-1 Order Part Number Coding Table 0-2 lists the part number coding based on the package. Table 0-2 Part Number Coding Part Number MC9S12UF32PB MC9S12UF32PU Package 64LQFP 100LQFP Description MC9S12UF32 Freescale Semiconductor Section 1 Introduction System on a Chip Guide 9S12UF32DGV1/D V01.05 Overview The MC9S12UF32 microcontroller unit MCU is USB2.0 device for memory card reader and ATA/ATAPI interface applications. This device is composed of standard on-chip modules including a 16-bit central processing unit HCS12 CPU , 32k bytes of Flash EEPROM, 3.5k bytes of RAM, USB2.0 interface, Integrated Queue Controller IQUE block with 1.5k bytes RAM buffer for USB Bulk data transport, ATA5 interface, Compact Flash interface, SD/MMC interface, SmartMedia interface, Memorystick interface, a 16-bit 8-channel timer, Serial Communication Interface, 73 discrete digital I/O channels and 2 input only channels1. The MC9S12UF32 has full 16-bit internal data paths throughout. • HCS12 Core 16-bit HCS12 CPU i. Upward compatible with M68HC11 instruction set ii. Interrupt stacking and programmer’s model identical to M68HC11 iii. Instruction queue iv. Enhanced indexed addressing Multiplexed External Bus Interface MEBI Memory Mapping Control MMC Interrupt Control INT Single-wire Background Debug Mode BDM On-chip hardware Breakpoints BKP • Clock and Reset Generator CRG_U Clock Throttle to prescale the oscillator clock or 60Mhz clock from USB20D6E2F. COP watchdog Real Time Interrupt • Memory 32K Flash EEPROM - Internal program/erase voltage generation - Security and Block Protect bits 3.5K byte RAM NOTES Not all functions are available simultaneously. Freescale Semiconductor System on a Chip Guide 9S12UF32DGV1/D V01.05 - Used as a contiguous 3.5k byte SRAM with misaligned access support - Configurable to 1084 byte SRAM and 2000 x 10 bit SRAM for Smartmedia logical to physical address translation and parity generation/checking support. 1.5K byte Queue RAM - SRAM used as USB endpoint buffer, access is arbitrated by IQUE module • 8-channel Timer TIM Eight input capture/output compare channels Clock prescaling 16-bit counter 16-bit pulse accumulator • Serial Interface Asynchronous serial communication interface SCI • Internal Regulator VREG_U Input voltage range from 4.25V to 5.5V Separate Regulation circuits - 2.5V Regulator for Core Logic and memory - 3.3V Regulator for USB2.0 physical layer interface - 3.3V Regulator with off-chip NMOS driver for I/O and memory cards Power on Reset detection • Integrated Queue Controller IQUE Provide block data transfer without CPU intervention Four independent queue channels for data transfer between Queue RAM and peripherals Unified Queue RAM Memory which can be allocated to different usb endpoints and storage interface module Programming model allows implementation of double buffering for maximum burst data throughput of 60M bytes per second between USB20D6E2F and one of the Storage Interfaces • Universal Serial Bus USB20D6E2F Intergrated USB2.0 Physical Layer Transceiver USB20PHY for High speed and Full Speed operations USB Serial Interface Engine USB20SIE for High Speed and Full Speed operations compatible - Endpoint 0 for Control IN and OUT operation - Endpoint 2 and 3 are configurable for Bulk, ISO or Interrupt IN/OUT operation - Endpoint buffer with programmable size residing in Queue RAM for endpoints 4 and 5 Freescale Semiconductor System on a Chip Guide 9S12UF32DGV1/D V01.05 - Endpoint 0 IN, endpoint 0 OUT, endpoint 2 and endpoint 3 each has an independent 64 bytes fixed endpoint buffer. • ATA5 Host Controller Interface ATA5HC Support PIO mode 0 to 4 Support Multi-word DMA mode 0 to 2 Support UDMA mode 0 to 4 Up to 60M Bytes/sec at UDMA mode 4 Sector data can be transferred to and from USB endpoint buffer without CPU intervention using IQUE module • Compact Flash Host Controller Interface CFHC Support Compact Flash memory and I/O mode access operations per CFA specification Sector data can be transferred to and from USB endpoint buffer without CPU intervention using IQUE module • Secure Digital and Multimedia Card Host Controller Interface SDHC Compatible with the MMC System Specification Version Compatible with the SD Memory Card Specification Sector data can be transferred to and from USB endpoint buffer without CPU intervention using IQUE module • Smartmedia Host Controller Interface SMHC Compatible with SmartMedia Specification Support SmartMedia with memory size of 4M Bytes to 128M Bytes Sector data can be transferred to and from USB endpoint buffer without CPU intervention using IQUE module • Memorystick Host Controller Interface MSHC 1 Compatible with Memory Stick Standard Sector data can be transferred to and from USB endpoint buffer without CPU intervention using IQUE module • Two Asynchronous External Interrupt pins XIRQ IRQ2 • 100-Pin LQFP package Up to 6 I/O pins with 5V only drive capability and 2 input only 5V pins. Up to 67 I/O pins with 3.3V/5V input and drive capability. NOTES The Document for the Memory Stick Host Controller in the 912UF32 will be available to users who have obtained a formal license of Memory Stick from Sony. Memory Stick is a Sony technology. IRQ is not available in 64 pin device. Freescale Semiconductor System on a Chip Guide 9S12UF32DGV1/D V01.05 • 64-Pin LQFP package User selectable subset of modules available. Up to 6 I/O pins with 5V only drive capability and 1 input only 5V pin. Up to 35 I/O pins with 3.3V/5V input and drive capability. • Operating frequency Maximum 60MHz equivalent to 30MHz CPU Bus Speed for single chip modes. 60MHz operation for IQUE module and storage interface modules attached to IQUE. Modes of Operation • Normal modes Normal Single-Chip Mode Normal Expanded Wide Mode Normal Expanded Narrow Mode Emulation Expanded Wide Mode Emulation Expanded Narrow Mode • Special Operating Modes Special Single-Chip Mode with active Background Debug Mode Special Test Mode Freescale use only Special Peripheral Mode Freescale use only • Each of the above modes of operation can be configured for two Low power sub-modes Stop Mode Wait Mode • Secure operation, preventing the unauthorized read and write of the flash memory contents. Freescale Semiconductor System on a Chip Guide 9S12UF32DGV1/D V01.05

PDF Datasheet Preview

MC9S12UF32 System on a Chip Guide

V01.05

TSPG - 8/16 Bit MCU Design, HKG Freescale Semiconductor, Inc.

This product has been designed for use in “Commercial” applications. Please see a description below. Freescale’s semiconductor products are classified into the following three tiers “Commercial”, “Industrial”, and “Automotive”. A product should only be used in applications appropriate to its tier. The recommended applications for products in the different tiers are indicated below. For questions, please contact a Freescale sales representative. Commercial Typically 5 year applications - personal computers, PDA’s, portable telecom products, consumer electronics, etc. Industrial Typically 10 year applications - installed telecom equipment, work stations, servers, etc. These products can also be used for Commercial applications. Automotive Qualified per automotive industry standard methods.

Release Number
17JAN02
19FEB02
26APR02
16SEP02
25SEP02
03JUN03
11JUN03 13JUL03

Author Y.H. Cheng Y.H. Cheng Y.H. Cheng Y.H. Cheng Y.H. Cheng

Y.H. Cheng

Y.H. Cheng Y.H. Cheng

Summary of Changes

Initial Version

Device pinout to separate D+ D- for high speed and low speed operation. Remap Timer pins to Port R. Update BG references.

Device pinout per IP requirement Add SCI Update Interrupt information.

Change pin location for REF3V and VREGEN minor update on module name references remove references to pseudo stop and clock monitor
- Updated info for SMRAM3P5K2E in device memory map - Updated EXTAL and XTAL supply rail information. - Relocate SCI module base address from to - Relocate ATA5HC module base address from to - Relocate PIM module base address from to - Relocate Interrupt Vectors - Updated Phy evaluation pinout. - Updated CFA00, CFA01 and CFA02 pin name to CFA0, CFA1 and CFA2 respectively. - Removed ESD and Latchup section in Electrical. - Update Block Guide References - Miscellaneous Typo mistakes.
- Update typo in interrupt vector table for Vector - Update typo in pin order of IOC[7:4] in signal properties table - Specify run and wait IDDs in Electrical Section - Specify stop IDD at room temperature in Electrical Section
- Change to include 64 pin option - ROMCTL pin assigned to PJ2

Freescale Semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Freescale Semiconductor does not assume any liability arising out of the application or use of any product or circuit described herein neither does it convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. FreescaleTM and the Freescale logo are registered trademarks of Freescale Semiconductor, Inc. Freescale Semiconductor, Inc. is an Equal Opportunity/Affirmative Action Employer.

Freescale Semiconductor, Inc. 2004

Freescale Semiconductor

Release Number
21AUG03
28NOV03
23MAR04 20APR04 10MAY04 03DEC04

Author

Y.H. Cheng

Wai-On Law Y.H. Cheng Wai-On Law Wai-On Law Wai-On Law

System on a Chip Guide 9S12UF32DGV1/D V01.05

Summary of Changes
- Removed all references to XCLKS, since function is removed. - typo - replaced PRU with RPU. - typo - replaced ATAHC with ATA5HC - Removed references to clock monitor, since function is not available. - Update for 100-pin and 64-pin packages. - Add footnotes on IRQ pin removal in 64-pin package - Update Flash memory map out of reset. - Add information on INITRM, INITRG, INITEE setting for example application memory map - Update clock distribution diagram to make it more intelligible - Change table 2-3, 2-5 description using general purpose port references instead of Functional module references. - Stop IDD spec for -40C and 85C are removed - Add other conditions for RUN Idd and Wait Idd.
- Minor typo corrections. - Corrected ‘Background Debug Module’ to ‘HCS12 Breakpoint’ at address in table - Added detailed register map. - Corrected the MSHC enable control in table - Added part ID for mask 1L47S.
- Removed all references and description on USB Physical Endpoint 6 - Updated IDD, 3V and 5V I/O electricals and package thermal resistance information - Include Commercial tier note - Update and add note to detailed register map.
- Added PIM reference.
- Added package information as appendix B.
- Improved - Fixed consistency of 3.0v and 3.3v for VDD3X. - Updated power dissipation formula. - Added schematic and PCB layout recommendations. - Added NVM, VREGU, CRGU electricals to appendix A.
Figure 0-1 provides an ordering number example.

MC9S12 UF32 FU

Package Option Device Title Controller Family

Package Options PB = 64LQFP PU = 100LQFP

Figure 0-1 Order Part Number Coding

Table 0-2 lists the part number coding based on the package. Table 0-2 Part Number Coding

Part Number MC9S12UF32PB MC9S12UF32PU

Package 64LQFP 100LQFP

Description MC9S12UF32

Freescale Semiconductor

Section 1 Introduction

System on a Chip Guide 9S12UF32DGV1/D V01.05

Overview

The MC9S12UF32 microcontroller unit MCU is USB2.0 device for memory card reader and ATA/ATAPI interface applications. This device is composed of standard on-chip modules including a 16-bit central processing unit HCS12 CPU , 32k bytes of Flash EEPROM, 3.5k bytes of RAM, USB2.0 interface, Integrated Queue Controller IQUE block with 1.5k bytes RAM buffer for USB Bulk data transport, ATA5 interface, Compact Flash interface, SD/MMC interface, SmartMedia interface, Memorystick interface, a 16-bit 8-channel timer, Serial Communication Interface, 73 discrete digital I/O channels and 2 input only channels1. The MC9S12UF32 has full 16-bit internal data paths throughout.
• HCS12 Core 16-bit HCS12 CPU i. Upward compatible with M68HC11 instruction set ii. Interrupt stacking and programmer’s model identical to M68HC11 iii. Instruction queue iv. Enhanced indexed addressing Multiplexed External Bus Interface MEBI Memory Mapping Control MMC Interrupt Control INT Single-wire Background Debug Mode BDM On-chip hardware Breakpoints BKP
• Clock and Reset Generator CRG_U Clock Throttle to prescale the oscillator clock or 60Mhz clock from USB20D6E2F. COP watchdog Real Time Interrupt
• Memory 32K Flash EEPROM - Internal program/erase voltage generation - Security and Block Protect bits 3.5K byte RAM

NOTES Not all functions are available simultaneously.

Freescale Semiconductor

System on a Chip Guide 9S12UF32DGV1/D V01.05
- Used as a contiguous 3.5k byte SRAM with misaligned access support - Configurable to 1084 byte SRAM and 2000 x 10 bit SRAM for Smartmedia logical to physical
address translation and parity generation/checking support. 1.5K byte Queue RAM
- SRAM used as USB endpoint buffer, access is arbitrated by IQUE module
• 8-channel Timer TIM

Eight input capture/output compare channels Clock prescaling 16-bit counter 16-bit pulse accumulator
• Serial Interface Asynchronous serial communication interface SCI
• Internal Regulator VREG_U Input voltage range from 4.25V to 5.5V Separate Regulation circuits
- 2.5V Regulator for Core Logic and memory - 3.3V Regulator for USB2.0 physical layer interface - 3.3V Regulator with off-chip NMOS driver for I/O and memory cards Power on Reset detection
• Integrated Queue Controller IQUE Provide block data transfer without CPU intervention Four independent queue channels for data transfer between Queue RAM and peripherals Unified Queue RAM Memory which can be allocated to different usb endpoints and storage interface module Programming model allows implementation of double buffering for maximum burst data throughput of 60M bytes per second between USB20D6E2F and one of the Storage Interfaces
• Universal Serial Bus USB20D6E2F Intergrated USB2.0 Physical Layer Transceiver USB20PHY for High speed and Full Speed operations USB Serial Interface Engine USB20SIE for High Speed and Full Speed operations compatible - Endpoint 0 for Control IN and OUT operation - Endpoint 2 and 3 are configurable for Bulk, ISO or Interrupt IN/OUT operation - Endpoint buffer with programmable size residing in Queue RAM for endpoints 4 and 5

Freescale Semiconductor

System on a Chip Guide 9S12UF32DGV1/D V01.05
- Endpoint 0 IN, endpoint 0 OUT, endpoint 2 and endpoint 3 each has an independent 64 bytes fixed endpoint buffer.
• ATA5 Host Controller Interface ATA5HC Support PIO mode 0 to 4 Support Multi-word DMA mode 0 to 2 Support UDMA mode 0 to 4 Up to 60M Bytes/sec at UDMA mode 4 Sector data can be transferred to and from USB endpoint buffer without CPU intervention using IQUE module
• Compact Flash Host Controller Interface CFHC Support Compact Flash memory and I/O mode access operations per CFA specification Sector data can be transferred to and from USB endpoint buffer without CPU intervention using IQUE module
• Secure Digital and Multimedia Card Host Controller Interface SDHC Compatible with the MMC System Specification Version Compatible with the SD Memory Card Specification Sector data can be transferred to and from USB endpoint buffer without CPU intervention using IQUE module
• Smartmedia Host Controller Interface SMHC Compatible with SmartMedia Specification Support SmartMedia with memory size of 4M Bytes to 128M Bytes Sector data can be transferred to and from USB endpoint buffer without CPU intervention using IQUE module
• Memorystick Host Controller Interface MSHC 1 Compatible with Memory Stick Standard Sector data can be transferred to and from USB endpoint buffer without CPU intervention using IQUE module
• Two Asynchronous External Interrupt pins XIRQ IRQ2
• 100-Pin LQFP package Up to 6 I/O pins with 5V only drive capability and 2 input only 5V pins. Up to 67 I/O pins with 3.3V/5V input and drive capability.

NOTES The Document for the Memory Stick Host Controller in the 912UF32 will be available to users who have obtained a formal
license of Memory Stick from Sony. Memory Stick is a Sony technology. IRQ is not available in 64 pin device.

Freescale Semiconductor

System on a Chip Guide 9S12UF32DGV1/D V01.05
• 64-Pin LQFP package User selectable subset of modules available. Up to 6 I/O pins with 5V only drive capability and 1 input only 5V pin. Up to 35 I/O pins with 3.3V/5V input and drive capability.
• Operating frequency Maximum 60MHz equivalent to 30MHz CPU Bus Speed for single chip modes. 60MHz operation for IQUE module and storage interface modules attached to IQUE.

Modes of Operation
• Normal modes Normal Single-Chip Mode Normal Expanded Wide Mode Normal Expanded Narrow Mode Emulation Expanded Wide Mode Emulation Expanded Narrow Mode
• Special Operating Modes Special Single-Chip Mode with active Background Debug Mode Special Test Mode Freescale use only Special Peripheral Mode Freescale use only
• Each of the above modes of operation can be configured for two Low power sub-modes Stop Mode Wait Mode
• Secure operation, preventing the unauthorized read and write of the flash memory contents.

Freescale Semiconductor

System on a Chip Guide 9S12UF32DGV1/D V01.05

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived MC9S12UF32PU Datasheet file may be downloaded here without warranties.

Datasheet ID: MC9S12UF32PU 635512