MC9S12DP512CPV

MC9S12DP512CPV Datasheet

MC9S12DP512 Device Guide

Part	Datasheet
MC9S12DP512CPV	MC9S12DP512CPV (pdf)

Related Parts	Information
MC9S12DP512CPVER	MC9S12DP512CPVER
MC9S12DP512CPVE	MC9S12DP512CPVE
MC9S12DP512VPVE	MC9S12DP512VPVE
MC9S12A512CPVE	MC9S12A512CPVE
MC9S12DP512MPVE	MC9S12DP512MPVE

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Freescale Semiconductor MC9S12DP512 Device Guide V01.25 DOCUMENT NUMBER 9S12DP512DGV1/D Covers also MC9S12DT512, MC9S12DJ512, MC9S12A512 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc., All rights reserved. DOCUMENT NUMBER 9S12DP512DGV1/D Number Date V01.00 27 Nov 2001 11 Feb 2002 V01.01 13 Mar 2002 13 Mar 2002 V01.02 V01.03 V01.04 02 Apr 2002 15 Apr 2002 06 Jun 2002 02 Apr 2002 15 Apr 2002 06 Jun 2002 V01.05 05 Jul 2002 05 Jul 2002 Author Description of Changes - Initial version based on DP256 V2.09. - Updated document formats. - Removed reference to SIM in overview. - Changed XCLKS to PE7 in signal description. - Removed "Oscillator start-up time from POR or STOP" from Oscillator Characterisitcs. - Changed VDD and VDDPLL to 2.35V. - Updated CINS. - Updated IOL/IOH values. - Updated input capacitance. - Updated NVM timing characteristics. - Updated document reference SPI, SCI . - Corrected values in device memory map RAM start, protected sector sizes . - Updated document reference SCI . - Changed all operating frequency references to 50MHz EXTAL and removed references to 80 pin LQFP. - Preface Table "Document References" Changed to full naming for each block. - Table "Interrupt Vector Locations", Column "Local Enable" Corrected several register and bit names. - Table "Signal Properties" Added column "Internal Pull Resistor". - Table "PLL Characteristics" Updated parameters K1 and f1 - Figure "Basic Pll functional diagram" Inserted XFC pin in diagram - Enhanced section "XFC Component Selection" - Added to Sections ATD, ECT and PWM freeze mode = active BDM mode. Freescale reserves the right to make changes without further notice to any products herein to improve reliability, function or design.Freescale does not assume any liability arising out of the application or use of any product or circuit described herein neither does it convey any license under its patent rights nor the rights of others.Freescale products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale was negligent regarding the design or manufacture of the part. MC9S12DP512 Device Guide V01.25 Number Date V01.06 24 Jul 2002 24 Jul 2002 V01.07 - Updated SPI electrical characteristics. - Updated Derivative Differences table. - Added ordering number example. - Added Detailed Register Map. - Changed Internal Pull Resistor column of signal table. - Added pull device description for MODC pin. - Corrected XCLKS titles. Moved table to section Modes of Operation. - Removed ’1/2’ from BDM in Figure Clock Connections. - Completely reworked section Modes of Operation. Added Chip Summary and Low Power Mode description. - Changed to C for internal pull currents inTable 5V I/O Characteristics. - Changed input leakage to 1uA for all pins. - Updated VREG section and layout recommendation. - Moved Power and Gound Connection Summary table to start of Power Supply Pins section. - Added ROMONE to pinout - Corrected mem map ’MEBI map x of 3’ - Corrected mem map KEYEN bits in FSEC. - Added section Printed Circuit Board Layout Proposal. - Corrected addresses in Reserved, CAN and EEP buffer map. - Updated NVM electricals. - Updated table ’Document References’ - Added section ’Oscillator OSC Block Description’ - Section HCS12 Core Block Desciption mentioned alternalte clock of BDM to be equivalent to oscillator clock - Corrected tables 0-1 and 0-2 - Added derivatives to cover sheet. - Added part ID for 1L00M maskset. - Corrected in footnote of Table "PLL Characteristics" fOSC = 4MHz. - Renamed Preface section to Derivative Differences and Document references. - Added A512 derivative. - Updated module set of DJ512 in Table - Added details for derivatives without CAN and/or BDLC modules. - Corrected several entries in ’Detailed Memory Map’. - Removed footnote on input leakage current from table ’5V I/O Characteristics’. - Updated section ’Unsecuring the Microcontroller’. - Updated footnote 1 in table ’Operating Conditions’. - Renamed ROMONE pin to ROMCTL. - Corrected PE[1,0] pull in Signal Properties Summary Table. MC9S12DP512 Device Guide V01.25 Number Date V01.16 31 Mar 2003 31 Mar 2003 V01.17 30 May 2003 30 May 2003 V01.18 V01.19 23 Jul 2003 24 Jul 2003 23 Jul 2003 24 Jul 2003 V01.20 01 Sep 2003 01 Sep 2003 V01.21 V01.22 V01.23 V01.24 V01.25 08 Mar 2004 23 Aug 2004 09 Feb 2005 01 Apr 2005 05 Jul 2005 08 Mar 2004 23 Aug 2004 09 Feb 2005 01 Apr 2005 05 Jul 2005 Author Description of Changes - Corrections in App. A ’NVM, Flash and EEPROM’ - Number of words per row = 64 - Replaced ’burst programming’ with ’row programming’ - Sector erase size = 1024 bytes - Corrected feature description ECT - Corrected min. bus freq. in table ’Operating Conditions’ - Replaced references to HCS12 Core Guide with the individual HCS12 Block guides throughout document - Table ’Absolute Maximum Ratings’ corrected footnote on clamp of TEST pin - Mentioned ’S12 LRAE’ bootloader in Flash section - Document References corrected S12 CPU document reference - Added part ID for 2L00M maskset. - Added part ID for 3L00M maskset. - Added cycle to ’CPU 12 Block Description’. - Diagram ’Clock Connections’ Connected Bus Clock to HCS12 Core. - Corrected ’Background Debug Module’ to ’HCS12 Breakpoint’ at address - in table - Corrected ’Blank Check Time Flash’ value in table ’NVM Timing Characteristics’ - Added EXTAL pin VIH, VIL and EXTAL pin hysteresis value to ’Oscillator Characteristics’. Updated oscillator description and table note. - Added part ID for 4L00M maskset. - Corrected pin name KWP5 in device pinout. The following figure provides an ordering number example for the MC9S12D-Family devices. MC9S12 DP512 C PV Package Option Temperature Option Device Title Controller Family Temperature Options C = to V = to M = to Package Options FU = 80 QFP PV = 112 LQFP Figure 0-1 Order Part Number Example MC9S12DP512 Device Guide V01.25 The following items should be considered when using a derivative Table 0-1 : • Registers Do not write or read CAN0 registers after reset address range - if using a derivative without CAN0. Do not write or read CAN1registers after reset address range - if using a derivative without CAN1. Do not write or read CAN2 registers after reset address range - if using a derivative without CAN2. Do not write or read CAN3 registers after reset address range - if using a derivative without CAN3. Do not write or read CAN4 registers after reset address range - if using a derivative without CAN4. Do not write or read BDLC registers after reset address range - if using a derivative without BDLC. • Interrupts Fill the four CAN0 interrupt vectors - according to your coding policies for unused interrupts, if using a derivative without CAN0. Fill the four CAN1 interrupt vectors - according to your coding policies for unused interrupts, if using a derivative without CAN1. Fill the four CAN2 interrupt vectors - according to your coding policies for unused interrupts, if using a derivative without CAN2. Fill the four CAN3 interrupt vectors - according to your coding policies for unused interrupts, if using a derivative without CAN3. Fill the four CAN4 interrupt vectors - according to your coding policies for unused interrupts, if using a derivative without CAN4. Fill the BDLC interrupt vector according to your coding policies for unused interrupts, if using a derivative without BDLC. • Ports The CAN0 pin functionality TXCAN0, RXCAN0 is not available on port PJ7, PJ6, PM5, PM4, PM3, PM2, PM1 and PM0, if using a derivative without CAN0. The CAN1 pin functionality TXCAN1, RXCAN1 is not available on port PM3 and PM2, if using a derivative without CAN1. The CAN2 pin functionality TXCAN2, RXCAN2 is not available on port PM5 and PM4, if using a derivative without CAN2. The CAN3 pin functionality TXCAN3, RXCAN3 is not available on port PM7 and PM6, if using a derivative without CAN3. MC9S12DP512 Device Guide V01.25 The CAN4 pin functionality TXCAN4, RXCAN4 is not available on port PJ7, PJ6, PM7, PM6, PM5 and PM4, if using a derivative without CAN0. The BDLC pin functionality TXB, RXB is not available on port PM1 and PM0, if using a derivative without BDLC. Do not write MODRR1 and MODRR0 bits of Module Routing Register PIM_9DP256 Block Guide , if using a derivative without CAN0. Do not write MODRR3 and MODRR2 bits of Module Routing Register PIM_9DP256 Block Guide , if using a derivative without CAN4. Document References The Device Guide provides information about the MC9S12DP512 device made up of standard HCS12 blocks and the HCS12 processor core. This document is part of the customer documentation. A complete set of device manuals also includes the individual Block Guides of the implemented modules. In an effort to reduce redundancy, all module specific information is located only in the respective Block Guide. If applicable, special implementation details of the module are given in the block description sections of this document. See Table 0-2 for names and versions of the referenced documents throughout the Device Guide. Table 0-2 Document References Block Guide Version HCS12 CPU Reference Manual

PDF Datasheet Preview

Freescale Semiconductor

MC9S12DP512 Device Guide

V01.25

DOCUMENT NUMBER 9S12DP512DGV1/D

Covers also

MC9S12DT512, MC9S12DJ512, MC9S12A512

Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc., All rights reserved.

DOCUMENT NUMBER 9S12DP512DGV1/D

Number Date

V01.00
27 Nov 2001
11 Feb 2002

V01.01
13 Mar 2002
13 Mar 2002

V01.02 V01.03 V01.04
02 Apr 2002
15 Apr 2002
06 Jun 2002
02 Apr 2002
15 Apr 2002
06 Jun 2002

V01.05
05 Jul 2002
05 Jul 2002

Author

Description of Changes
- Initial version based on DP256 V2.09.
- Updated document formats. - Removed reference to SIM in overview. - Changed XCLKS to PE7 in signal description. - Removed "Oscillator start-up time from POR or STOP" from Oscillator Characterisitcs. - Changed VDD and VDDPLL to 2.35V. - Updated CINS. - Updated IOL/IOH values. - Updated input capacitance. - Updated NVM timing characteristics.
- Updated document reference SPI, SCI .
- Corrected values in device memory map RAM start, protected sector sizes . - Updated document reference SCI .
- Changed all operating frequency references to 50MHz EXTAL and removed references to 80 pin LQFP.
- Preface Table "Document References" Changed to full naming for each block. - Table "Interrupt Vector Locations", Column "Local Enable" Corrected several register and bit names. - Table "Signal Properties" Added column "Internal Pull Resistor". - Table "PLL Characteristics" Updated parameters K1 and f1 - Figure "Basic Pll functional diagram" Inserted XFC pin in diagram - Enhanced section "XFC Component Selection" - Added to Sections ATD, ECT and PWM freeze mode = active BDM mode.

Freescale reserves the right to make changes without further notice to any products herein to improve reliability, function or design.Freescale does not assume any liability arising out of the application or use of any product or circuit described herein neither does it convey any license under its patent rights nor the rights of others.Freescale products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale was negligent regarding the design or manufacture of the part.

MC9S12DP512 Device Guide V01.25

Number Date

V01.06
24 Jul 2002
24 Jul 2002

V01.07
- Updated SPI electrical characteristics. - Updated Derivative Differences table. - Added ordering number example. - Added Detailed Register Map. - Changed Internal Pull Resistor column of signal table. - Added pull device description for MODC pin. - Corrected XCLKS titles. Moved table to section Modes of Operation. - Removed ’1/2’ from BDM in Figure Clock Connections. - Completely reworked section Modes of Operation. Added Chip Summary and Low Power Mode description. - Changed to C for internal pull currents inTable 5V I/O Characteristics. - Changed input leakage to 1uA for all pins. - Updated VREG section and layout recommendation. - Moved Power and Gound Connection Summary table to start of Power Supply Pins section. - Added ROMONE to pinout
- Corrected mem map ’MEBI map x of 3’ - Corrected mem map KEYEN bits in FSEC. - Added section Printed Circuit Board Layout Proposal. - Corrected addresses in Reserved, CAN and EEP buffer map. - Updated NVM electricals.
- Updated table ’Document References’ - Added section ’Oscillator OSC Block Description’
- Section HCS12 Core Block Desciption mentioned alternalte clock of BDM to be equivalent to oscillator clock - Corrected tables 0-1 and 0-2
- Added derivatives to cover sheet. - Added part ID for 1L00M maskset. - Corrected in footnote of Table "PLL Characteristics" fOSC = 4MHz.
- Renamed Preface section to Derivative Differences and Document references. - Added A512 derivative. - Updated module set of DJ512 in Table - Added details for derivatives without CAN and/or BDLC modules.
- Corrected several entries in ’Detailed Memory Map’. - Removed footnote on input leakage current from table ’5V I/O Characteristics’.
- Updated section ’Unsecuring the Microcontroller’. - Updated footnote 1 in table ’Operating Conditions’.
- Renamed ROMONE pin to ROMCTL.
- Corrected PE[1,0] pull in Signal Properties Summary Table.

MC9S12DP512 Device Guide V01.25

Number Date

V01.16
31 Mar 2003
31 Mar 2003

V01.17
30 May 2003
30 May 2003

V01.18 V01.19
23 Jul 2003
24 Jul 2003
23 Jul 2003
24 Jul 2003

V01.20
01 Sep 2003
01 Sep 2003

V01.21 V01.22 V01.23 V01.24 V01.25
08 Mar 2004
23 Aug 2004
09 Feb 2005 01 Apr 2005 05 Jul 2005
08 Mar 2004
23 Aug 2004
09 Feb 2005 01 Apr 2005 05 Jul 2005

Author

Description of Changes
- Corrections in App. A ’NVM, Flash and EEPROM’ - Number of words per row = 64 - Replaced ’burst programming’ with ’row programming’ - Sector erase size = 1024 bytes - Corrected feature description ECT - Corrected min. bus freq. in table ’Operating Conditions’
- Replaced references to HCS12 Core Guide with the individual HCS12 Block guides throughout document - Table ’Absolute Maximum Ratings’ corrected footnote on clamp of TEST pin
- Mentioned ’S12 LRAE’ bootloader in Flash section - Document References corrected S12 CPU document reference
- Added part ID for 2L00M maskset.
- Added part ID for 3L00M maskset. - Added cycle to ’CPU 12 Block Description’. - Diagram ’Clock Connections’ Connected Bus Clock to HCS12 Core. - Corrected ’Background Debug Module’ to ’HCS12 Breakpoint’ at address - in table - Corrected ’Blank Check Time Flash’ value in table ’NVM Timing Characteristics’ - Added EXTAL pin VIH, VIL and EXTAL pin hysteresis value to ’Oscillator Characteristics’. Updated oscillator description and table note.
- Added part ID for 4L00M maskset. - Corrected pin name KWP5 in device pinout.
The following figure provides an ordering number example for the MC9S12D-Family devices.

MC9S12 DP512 C PV

Package Option Temperature Option Device Title Controller Family

Temperature Options

C = to V = to M = to

Package Options FU = 80 QFP PV = 112 LQFP

Figure 0-1 Order Part Number Example

MC9S12DP512 Device Guide V01.25

The following items should be considered when using a derivative Table 0-1 :
• Registers

Do not write or read CAN0 registers after reset address range - if using a derivative without CAN0.

Do not write or read CAN1registers after reset address range - if using a derivative without CAN1.

Do not write or read CAN2 registers after reset address range - if using a derivative without CAN2.

Do not write or read CAN3 registers after reset address range - if using a derivative without CAN3.

Do not write or read CAN4 registers after reset address range - if using a derivative without CAN4.

Do not write or read BDLC registers after reset address range - if using a derivative without BDLC.
• Interrupts

Fill the four CAN0 interrupt vectors - according to your coding policies for unused interrupts, if using a derivative without CAN0.

Fill the four CAN1 interrupt vectors - according to your coding policies for unused interrupts, if using a derivative without CAN1.

Fill the four CAN2 interrupt vectors - according to your coding policies for unused interrupts, if using a derivative without CAN2.

Fill the four CAN3 interrupt vectors - according to your coding policies for unused interrupts, if using a derivative without CAN3.

Fill the four CAN4 interrupt vectors - according to your coding policies for unused interrupts, if using a derivative without CAN4.

Fill the BDLC interrupt vector according to your coding policies for unused interrupts, if using a derivative without BDLC.
• Ports

The CAN0 pin functionality TXCAN0, RXCAN0 is not available on port PJ7, PJ6, PM5, PM4, PM3, PM2, PM1 and PM0, if using a derivative without CAN0.

The CAN1 pin functionality TXCAN1, RXCAN1 is not available on port PM3 and PM2, if using a derivative without CAN1.

The CAN2 pin functionality TXCAN2, RXCAN2 is not available on port PM5 and PM4, if using a derivative without CAN2.

The CAN3 pin functionality TXCAN3, RXCAN3 is not available on port PM7 and PM6, if using a derivative without CAN3.

MC9S12DP512 Device Guide V01.25

The CAN4 pin functionality TXCAN4, RXCAN4 is not available on port PJ7, PJ6, PM7, PM6, PM5 and PM4, if using a derivative without CAN0.

The BDLC pin functionality TXB, RXB is not available on port PM1 and PM0, if using a derivative without BDLC.

Do not write MODRR1 and MODRR0 bits of Module Routing Register PIM_9DP256 Block Guide , if using a derivative without CAN0.

Do not write MODRR3 and MODRR2 bits of Module Routing Register PIM_9DP256 Block Guide , if using a derivative without CAN4.

Document References

The Device Guide provides information about the MC9S12DP512 device made up of standard HCS12 blocks and the HCS12 processor core.

This document is part of the customer documentation. A complete set of device manuals also includes the individual Block Guides of the implemented modules. In an effort to reduce redundancy, all module specific information is located only in the respective Block Guide. If applicable, special implementation details of the module are given in the block description sections of this document.

See Table 0-2 for names and versions of the referenced documents throughout the Device Guide.

Table 0-2 Document References

Block Guide

Version

HCS12 CPU Reference Manual

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived MC9S12DP512CPV Datasheet file may be downloaded here without warranties.

Datasheet ID: MC9S12DP512CPV 635508