MC100ES6535DT
MC100ES6535DT Datasheet
Order number MC100ES6535 Rev 2, 05/2004
| Part | Datasheet |
|---|---|
MC100ES6535DT |
MC100ES6535DT (pdf) |
| PDF Datasheet Preview |
|---|
| Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. MOTOROLA SEMICONDUCTOR TECHNICAL DATA 3.3V LVCMOS to LVPECL 1:4 Fanout Buffer The MC100ES6535 is a low skew, high performance V 1-to-4 LVCMOS to LVPECL fanout buffer. The ES6535 has two selectable inputs that allow LVCMOS or LVTTL input levels which translate to LVPECL outputs. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/ deassertion of the clock enable pin. The ES6535 is ideal for high performance clock distribution applications. MC100ES6535 Features • 4 differential LVPECL outputs • 2 selectable LVCMOS/LVTTL inputs • 1 GHz maximum output frequency • Translates LVCMOS/LVTTL levels to LVPECL levels • 30 ps maximum output skew • 190 ps part-to-part skew • V operating range • 20-lead TSSOP package • Ambient temperature range -40°C to +85°C DT SUFFIX 20-LEAD TSSOP PACKAGE CASE 948E ORDERING INFORMATION Device MC100ES6535DT Package TSSOP-20 MC100ES6535DTR2 TSSOP-20 CLK_EN CLK0 CLK1 CLK_SEL Figure Logic Diagram CLK_EN 20 Q0 19 Q0 CLK_SEL CLK0 17 Q1 16 Q1 MC100ES6535 CLK1 15 Q2 14 Q2 11 Q3 Figure 20-Lead Pinout Top View Motorola, Inc. 2004 For More Information On This Product, Go to: Freescale Semiconductor, Inc... MC100ES6535 Freescale Semiconductor, Inc. Table PIN DESCRIPTION Number Name CLK_EN Type Power Input Pullupa CLK_SEL Input Pulldowna CLK0 Input Pulldowna CLK1 |
| More datasheets: SMDA24C-7/TR7 | SMDA15C-7/TR7 | SMDA05C-7/TR7 | CA3102R18-4SXF80 | DCMAM37SNMK52 | ICS954148AGLF | MDM-37SH026L | DBMN5H5SN | DDMM-50S-L | DDMY36W4SA191A197 |
Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived MC100ES6535DT Datasheet file may be downloaded here without warranties.