MC100ES6222TB

MC100ES6222TB Datasheet

MC100ES6222 Rev 4, 04/2005

Part	Datasheet
MC100ES6222TB	MC100ES6222TB (pdf)

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Freescale Semiconductor Technical Data Low Voltage 1:15 Differential ECL/PECL Clock Divider and Fanout Buffer MC100ES6222 The MC100ES6222 is a bipolar monolithic differential clock fanout buffer. Designed for most demanding clock distribution systems, the MC100ES6222 supports various applications that require the distribution of precisely aligned differential clock signals. Using SiGe technology and a fully differential architecture, the device offers very low skew outputs and superior digital signal characteristics. Target applications for this clock driver is high performance clock distribution in computing, networking and telecommunication systems. LOW-VOLTAGE 1:15 DIFFERENTIAL ECL/PECL CLOCK DIVIDER AND FANOUT DRIVER • 15 differential ECL/PECL outputs 4 output banks • 2 selectable differential ECL/PECL inputs • Selectable ÷1 or ÷2 frequency divider • 130 ps maximum device skew • Supports DC to 3 GHz input frequency • Single V, V, V or V supply • Standard 52-lead LQFP package with exposed pad for enhanced thermal characteristics • Supports industrial temperature range • Pin and function compatible to the MC100EP222 • 52-lead Pb-free Package Available Functional Description TB SUFFIX 52-LEAD LQFP PACKAGE EXPOSED PAD CASE 1336A-01 AE SUFFIX 52-LEAD LQFP PACKAGE Pb-FREE PACKAGE CASE 1336A-01 The MC100ES6222 is designed for low skew clock distribution systems and supports clock frequencies up to 3 GHz. The CLK0 and CLK1 inputs can be driven by ECL or PECL compatible signals. Each of the four output banks of two, three, four and six differential clock output pairs can be independently configured to distribute the input frequency or ÷2 of the input frequency. The FSELA, FSELB, FSELC, FSELD, and CLK_SEL are asychronous control inputs. Any changes of the control inputs require a MR pulse for resynchronization of the ÷2 outputs. For the functionality of the MR control input, see Figure Functional Diagram. In order to meet the tight skew specification of the device, both outputs of a differential output pair should be terminated, even if only one output is used. In the case where not all ten outputs are used, the output pairs on the same package side as the parts being used on that side should be terminated. The MC100ES6222 can be operated from a single V or V supply. As most other ECL compatible devices, the MC100ES6222 supports positive PECL and negative ECL supplies. The MC100ES6222 is pin and function compatible to the MC100EP222. Freescale Semiconductor, Inc., All rights reserved. FSELA VEE CLK0 CLK0 0 ÷1 CLK1 1 ÷2 VEE CLK_SEL VEE FSELB FSELC 0 VEE MR VEE FSELD QA0 QA1 39 38 37 36 35 34 33 32 31 30 29 28 27 QC0 QB1 QC1 QB0 QC2 QB0 QC3 QA1 MC100ES6222 QD0 QA1 QD1 QA0 1 2 3 4 5 6 7 8 9 10 11 12 13 FSELD FSELC CLK1 CLK1 CLK_SEL

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Freescale Semiconductor Technical Data

Low Voltage 1:15 Differential ECL/PECL Clock Divider and Fanout Buffer

MC100ES6222

The MC100ES6222 is a bipolar monolithic differential clock fanout buffer. Designed for most demanding clock distribution systems, the MC100ES6222 supports various applications that require the distribution of precisely aligned differential clock signals. Using SiGe technology and a fully differential architecture, the device offers very low skew outputs and superior digital signal characteristics. Target applications for this clock driver is high performance clock distribution in computing, networking and telecommunication systems.

LOW-VOLTAGE 1:15 DIFFERENTIAL ECL/PECL CLOCK DIVIDER AND FANOUT DRIVER
• 15 differential ECL/PECL outputs 4 output banks
• 2 selectable differential ECL/PECL inputs
• Selectable ÷1 or ÷2 frequency divider
• 130 ps maximum device skew
• Supports DC to 3 GHz input frequency
• Single V, V, V or V supply
• Standard 52-lead LQFP package with exposed pad for enhanced thermal
characteristics
• Supports industrial temperature range
• Pin and function compatible to the MC100EP222
• 52-lead Pb-free Package Available

Functional Description

TB SUFFIX 52-LEAD LQFP PACKAGE

EXPOSED PAD CASE 1336A-01

AE SUFFIX 52-LEAD LQFP PACKAGE

Pb-FREE PACKAGE CASE 1336A-01

The MC100ES6222 is designed for low skew clock distribution systems and supports clock frequencies up to 3 GHz. The CLK0 and CLK1 inputs can be driven by ECL or PECL compatible signals. Each of the four output banks of two, three, four and six differential clock output pairs can be independently configured to distribute the input frequency or ÷2 of the input frequency. The FSELA, FSELB, FSELC, FSELD, and CLK_SEL are asychronous control inputs. Any changes of the control inputs require a MR pulse for resynchronization of the ÷2 outputs. For the functionality of the MR control input, see Figure Functional Diagram.

In order to meet the tight skew specification of the device, both outputs of a differential output pair should be terminated, even if only one output is used. In the case where not all ten outputs are used, the output pairs on the same package side as the parts being used on that side should be terminated.

The MC100ES6222 can be operated from a single V or V supply. As most other ECL compatible devices, the MC100ES6222 supports positive PECL and negative ECL supplies. The MC100ES6222 is pin and function compatible to the MC100EP222.

Freescale Semiconductor, Inc., All rights reserved.

FSELA

VEE CLK0

CLK0
0 ÷1

CLK1
1 ÷2

VEE CLK_SEL

VEE FSELB FSELC
0 VEE MR

VEE FSELD

QA0 QA1
39 38 37 36 35 34 33 32 31 30 29 28 27

QC0 QB1

QC1 QB0

QC2 QB0

QC3 QA1

MC100ES6222

QD0 QA1

QD1 QA0
1 2 3 4 5 6 7 8 9 10 11 12 13

FSELD

FSELC

CLK1

CLK1

CLK_SEL

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Datasheet ID: MC100ES6222TB 635466