MC100ES6039DW

MC100ES6039DW Datasheet

The MC100ES6039 is a low skew ÷2/4, ÷4/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, LVPECL input signals. In addition, by using the VBB output, a sinusoidal source can be AC coupled into the device.

Part	Datasheet
MC100ES6039DW	MC100ES6039DW (pdf)

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Freescale Semiconductor Technical Data V ECL/PECL/HSTL/LVDS ÷2/4, ÷4/6 Clock Generation Chip The MC100ES6039 is a low skew ÷2/4, ÷4/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, LVPECL input signals. In addition, by using the VBB output, a sinusoidal source can be AC coupled into the device. The common enable EN is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. The internal enable flip-flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input. Upon startup, the internal flip-flops will attain a random state therefore, for systems which utilize multiple ES6039s, the master reset MR input must be asserted to ensure synchronization. For systems which only use one ES6039, the MR pin need not be exercised as the internal divider design ensures synchronization between the ÷2/4 and the ÷4/6 outputs of a single device. All VCC and VEE pins must be externally connected to power supply to guarantee proper operation. The 100ES Series contains temperature compensation. • Maximum Frequency GHz Typical • 50 ps Output-to-Output Skew • PECL Mode Operating Range VCC = V to V with VEE = 0 V • ECL Mode Operating Range VCC = 0 V with VEE = V to V • Open Input Default State • Synchronous Enable/Disable • Master Reset for Synchronization of Multiple Chips • VBB Output • LVDS and HSTL Input Compatible • 20-Lead Pb-Free Package Available MC100ES6039 DW SUFFIX 20-LEAD SOIC PACKAGE CASE 751D-07 EG SUFFIX 20-LEAD TSSOP PACKAGE Pb-FREE PACKAGE CASE 751D-07 ORDERING INFORMATION Device Package MC100ES6039DW SO-20 MC100ES6039DWR2 SO-20 MC100ES6039EG SO-20 Pb-Free MC100ES6039EGR2 SO-20 Pb-Free Freescale Semiconductor, Inc., All rights reserved. VCC Q0 Q1 Q2 Q3 VEE 20 19 18 17 16 15 14 13 12 11 DIVSELb DIVSELa 12 VCC EN 3 4 5 6 7 8 9 10 CLK VBB MR VCC NC Warning All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. Figure 20-Lead Pinout Top View DIVSELa CLK Table Pin Description Pin CLK 1 , CLK 1 EN 1 MR 1 VBB Q0, Q1, Q0, Q1 Q2, Q3, Q2, Q3 DIVSELa 1 DIVSELb 1 VCC VEE NC Function ECL Diff Clock Inputs ECL Sync Enable ECL Master Reset ECL Reference Output ECL Diff ÷2/4 Outputs ECL Diff ÷4/6 Outputs ECL Freq. Select Input ÷2/4 ECL Freq. Select Input ÷4/6 ECL Positive Supply ECL Negative Supply No Connect Pins will default low when left open. ÷2/4 Q0 MR DIVSELb ÷4/6 Q2 Figure Logic Diagram Table Function Tables X = Don’t Care Z = Low-to-High Transition ZZ = High-to-Low Transition DIVSELa L H DIVSELb Function Divide Hold Q0:3 Reset Q0:3 Q0:1 Outputs Divide by 2 Divide by 4 Q2:3 Outputs Divide by 4 Divide by 6 MC100ES6039 2 Advanced Clock Drivers Device Data Freescale Semiconductor CLK Q ÷2 Q ÷4 Q ÷6 Figure Timing Diagram

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Freescale Semiconductor Technical Data

V ECL/PECL/HSTL/LVDS ÷2/4, ÷4/6 Clock Generation Chip

The MC100ES6039 is a low skew ÷2/4, ÷4/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, LVPECL input signals. In addition, by using the VBB output, a sinusoidal source can be AC coupled into the device.

The common enable EN is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. The internal enable flip-flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input.

Upon startup, the internal flip-flops will attain a random state therefore, for systems which utilize multiple ES6039s, the master reset MR input must be asserted to ensure synchronization. For systems which only use one ES6039, the MR pin need not be exercised as the internal divider design ensures synchronization between the ÷2/4 and the ÷4/6 outputs of a single device. All VCC and VEE pins must be externally connected to power supply to guarantee proper operation.

The 100ES Series contains temperature compensation.
• Maximum Frequency GHz Typical
• 50 ps Output-to-Output Skew
• PECL Mode Operating Range VCC = V to V with VEE = 0 V
• ECL Mode Operating Range VCC = 0 V with VEE = V to V
• Open Input Default State
• Synchronous Enable/Disable
• Master Reset for Synchronization of Multiple Chips
• VBB Output
• LVDS and HSTL Input Compatible
• 20-Lead Pb-Free Package Available

MC100ES6039

DW SUFFIX 20-LEAD SOIC PACKAGE

CASE 751D-07

EG SUFFIX 20-LEAD TSSOP PACKAGE

Pb-FREE PACKAGE CASE 751D-07
ORDERING INFORMATION

Device

Package

MC100ES6039DW

SO-20

MC100ES6039DWR2

SO-20

MC100ES6039EG

SO-20 Pb-Free

MC100ES6039EGR2 SO-20 Pb-Free

Freescale Semiconductor, Inc., All rights reserved.

VCC Q0 Q1 Q2 Q3 VEE 20 19 18 17 16 15 14 13 12 11

DIVSELb DIVSELa
12 VCC EN
3 4 5 6 7 8 9 10 CLK VBB MR VCC NC

Warning All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation.

Figure 20-Lead Pinout Top View

DIVSELa CLK

Table Pin Description

Pin CLK 1 , CLK 1 EN 1 MR 1 VBB Q0, Q1, Q0, Q1 Q2, Q3, Q2, Q3 DIVSELa 1 DIVSELb 1 VCC VEE NC

Function ECL Diff Clock Inputs ECL Sync Enable ECL Master Reset ECL Reference Output ECL Diff ÷2/4 Outputs ECL Diff ÷4/6 Outputs ECL Freq. Select Input ÷2/4 ECL Freq. Select Input ÷4/6 ECL Positive Supply ECL Negative Supply No Connect

Pins will default low when left open.
÷2/4 Q0

MR DIVSELb
÷4/6 Q2

Figure Logic Diagram

Table Function Tables

X = Don’t Care Z = Low-to-High Transition ZZ = High-to-Low Transition

DIVSELa

L H DIVSELb

Function

Divide

Hold Q0:3

Reset Q0:3

Q0:1 Outputs

Divide by 2 Divide by 4 Q2:3 Outputs

Divide by 4 Divide by 6

MC100ES6039 2

Advanced Clock Drivers Device Data Freescale Semiconductor

CLK Q ÷2 Q ÷4 Q ÷6

Figure Timing Diagram

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Datasheet ID: MC100ES6039DW 635457