ZL30410QCG1

ZL30410QCG1 Datasheet

ZL30410 Multi-service Line Card PLL

Part	Datasheet
ZL30410QCG1	ZL30410QCG1 (pdf)

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ZL30410 Multi-service Line Card PLL Data Sheet • Generates clocks for OC-3, STM-1, DS3, E3, DS2, DS1, E1, MHz and ST-BUS • Meets jitter generation requirements for STM-1, OC-3, DS3, E3, J2 DS2 , E1 and DS1 interfaces • Compatible with GR-253-CORE SONET stratum 3 and G.813 SEC timing compliant clocks • Provides “hit-less” reference switching • Detects frequency of both reference clocks and synchronizes to any combination of 8 kHz, MHz, MHz and MHz reference frequencies • Continuously monitors both references for frequency accuracy exceeding ±12 ppm • Holdover accuracy of 70x10 -12 meets GR-1244 Stratum 3E and ITU-T G.812 requirements • Meets requirements of G.813 Option 1 for SDH Equipment Clocks SEC and GR-1244 for Stratum 4E and Stratum 4 Clocks • V power supply • Line Card synchronization for SDH, SONET, DS3, E3, J2 DS2 , E1 and DS1 interfaces • Timing card synchronization for SDH and PDH Network Elements November 2006 Ordering Information ZL30410QCC ZL30410QCG1 80 Pin LQFP Trays 80 Pin LQFP* Trays, Bake & Drypack *Pb Free Matte Tin -40°C to 85°C • Clock generation for ST-BUS and GCI timing The ZL30410 is a Multi-service Line Card Phase-Locked Loop designed to generate multiple clocks for SONET, SDH and PDH equipment including timing for ST-BUS and GCI interfaces. The ZL30410 operates in NORMAL LOCKED , HOLDOVER and FREE-RUN modes to ensure that in the presence of jitter and interruptions to the reference signals, the generated clocks meet international standards. The filtering characteristics of the PLL are hardware pin selectable and they do not require any external adjustable components. The ZL30410 uses an external 20 MHz Master Clock Oscillator to provide a stable timing source for the HOLDOVER operation. PRI PRIOR SEC SECOR RefSel RESET VDD GND Primary Acquisition Secondary Acquisition C20i Master Clock Frequency Calibration Core PLL APLL Clock Synthesizer Control State Machine JTAG IEEE 1149.1a MS1 MS2 RefAlign LOCK HOLDOVER Figure 1 - Functional Block Diagram Zarlink Semiconductor US Patent No. 5,602,884, UK Patent No. 0772912, France Brevete S.G.D.G. 0772912 Germany DBP No. 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003-2006, Zarlink Semiconductor Inc. All Rights Reserved. C155P/N C34/C44 C19o C16o C8o C6o C4o C2o C1.5o F16o F8o F0o E3DS3/OC3 E3/DS3 Tclk Tdi Tdo Tms Trst ZL30410 Data Sheet Table of Contents Change Summary 5 ZL30410 Pinout 5 Pin Connections 5 Functional Description 10 Acquisition PLLs 10 Core PLL 10 Digitally Controlled Oscillator DCO 11 Filters 11 Lock Indicator LOCK 11 Reference Alignment RefAlign . 11 Using RefAlign with MHz, MHz or MHz Reference 12 Using RefAlign with an 8 kHz Reference 12 Clock Synthesizer 12 Output Clocks. 12 Control State Machine 13 Clock Modes 13 ZL30410 State Machine 13 State Transitions 15 JTAG Interface 16 Control Interface 16 Control Pins 16 Status Pins 17 Applications 18 ZL30410 Switching Between Clock Modes 18 System Start-up Sequence FREE-RUN --> HOLDOVER --> NORMAL 18 Single Reference Operation NORMAL --> AUTO HOLDOVER --> NORMAL 19 Single 8 kHz Reference Operation NORMAL --> AUTO HOLDOVER--> HOLDOVER --> NORMAL 20 Dual Reference Operation NORMAL --> AUTO HOLDOVER--> HOLDOVER --> NORMAL. 20 Reference Switching RefSel NORMAL --> HOLDOVER --> NORMAL 21 Power Supply Filtering. 22 Characteristics 23 AC and DC Electrical Characteristics 23 Performance Characteristics 30 Zarlink Semiconductor Inc. ZL30410 Data Sheet Ordering Information Box Change Updated Ordering Information. ZL30410 Pinout Pin Connections IC NC LOCK NC HOLDOVER VDD C34/C44 GND C20i NC VDD RefAlign RefSel C19o GND IC C6o C1.5o PRIOR SECOR OE NC RESET NC IC GND IC VDD IC NC IC 60 58 56 54 52 50 48 46 44 42 40 62 38 64 36 66 34 68 32 ZL30410 72 28 74 26 76 24 78 22 80 2 4 6 8 10 12 14 16 18 20 NC Tdi Trst Tclk Tms Tdo NC GND C155P C155N VDD AVDD GND IC GND PRI SEC E3/DS3 E3DS3/OC3 IC NC GND NC FCS VDD GND F16o C16o C8o C4o C2o F0o MS1 MS2 F8o Figure 2 - Pin Connections for 80-pin LQFP package Zarlink Semiconductor Inc. Pin Description Pin # 1 2-5 6 7, 8 9 Name IC NC GND NC FCS F16o C16o ZL30410 Data Sheet Internal Connection. Leave unconnected. No internal bonding Connection. Leave unconnected. Ground. Negative power supply. No internal bonding Connection. Leave unconnected. Filter Characteristic Select Input . In Hardware Control, FCS selects the filtering characteristics of the ZL30410. Set this pin high to have a loop filter corner frequency of 6 Hz and limit the phase slope to 41 ns per ms. Set this pin low to have corner frequency of 12 Hz with no phase slope limiting imposed. This pin is internally pulled down to GND. Positive Power Supply Ground Frame Pulse ST-BUS Mbps CMOS tristate output . This is an 8 kHz, 61 ns wide, active low framing pulse, which marks beginning of a ST-BUS frame. This frame pulse is typically used for ST-BUS operation at Mbps. Clock MHz CMOS tristate output . This clock is used for ST-BUS operation at Mbps. Clock MHz CMOS tristate output . This clock is used for ST-BUS operation at Mbps. Clock MHz CMOS tristate output . This clock is used for ST-BUS operation at Mbps.

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ZL30410 Multi-service Line Card PLL

Data Sheet
• Generates clocks for OC-3, STM-1, DS3, E3, DS2, DS1, E1, MHz and ST-BUS
• Meets jitter generation requirements for STM-1, OC-3, DS3, E3, J2 DS2 , E1 and DS1 interfaces
• Compatible with GR-253-CORE SONET stratum 3 and G.813 SEC timing compliant clocks
• Provides “hit-less” reference switching
• Detects frequency of both reference clocks and
synchronizes to any combination of 8 kHz, MHz, MHz and MHz reference frequencies
• Continuously monitors both references for frequency accuracy exceeding ±12 ppm
• Holdover accuracy of 70x10 -12 meets GR-1244 Stratum 3E and ITU-T G.812 requirements
• Meets requirements of G.813 Option 1 for SDH Equipment Clocks SEC and GR-1244 for Stratum 4E and Stratum 4 Clocks
• V power supply
• Line Card synchronization for SDH, SONET, DS3, E3, J2 DS2 , E1 and DS1 interfaces
• Timing card synchronization for SDH and PDH Network Elements

November 2006
Ordering Information

ZL30410QCC ZL30410QCG1
80 Pin LQFP Trays 80 Pin LQFP* Trays, Bake & Drypack
*Pb Free Matte Tin
-40°C to 85°C
• Clock generation for ST-BUS and GCI timing

The ZL30410 is a Multi-service Line Card Phase-Locked Loop designed to generate multiple clocks for SONET, SDH and PDH equipment including timing for ST-BUS and GCI interfaces.

The ZL30410 operates in NORMAL LOCKED , HOLDOVER and FREE-RUN modes to ensure that in the presence of jitter and interruptions to the reference signals, the generated clocks meet international standards. The filtering characteristics of the PLL are hardware pin selectable and they do not require any external adjustable components. The ZL30410 uses an external 20 MHz Master Clock Oscillator to provide a stable timing source for the HOLDOVER operation.

PRI PRIOR

SEC SECOR

RefSel RESET

VDD GND

Primary Acquisition

Secondary Acquisition

C20i

Master Clock Frequency Calibration

Core PLL

APLL

Clock Synthesizer

Control State Machine

JTAG IEEE 1149.1a

MS1 MS2 RefAlign LOCK HOLDOVER

Figure 1 - Functional Block Diagram

Zarlink Semiconductor US Patent No. 5,602,884, UK Patent No. 0772912, France Brevete S.G.D.G. 0772912 Germany DBP No. 1

Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

Copyright 2003-2006, Zarlink Semiconductor Inc. All Rights Reserved.

C155P/N C34/C44 C19o C16o C8o C6o C4o C2o C1.5o F16o F8o F0o

E3DS3/OC3 E3/DS3

Tclk Tdi Tdo Tms Trst

ZL30410

Data Sheet

Table of Contents

Change Summary 5

ZL30410 Pinout 5 Pin Connections 5

Functional Description 10 Acquisition PLLs 10 Core PLL 10 Digitally Controlled Oscillator DCO 11 Filters 11 Lock Indicator LOCK 11 Reference Alignment RefAlign . 11 Using RefAlign with MHz, MHz or MHz Reference 12 Using RefAlign with an 8 kHz Reference 12 Clock Synthesizer 12 Output Clocks. 12 Control State Machine 13 Clock Modes 13 ZL30410 State Machine 13 State Transitions 15 JTAG Interface 16

Control Interface 16 Control Pins 16 Status Pins 17

Applications 18 ZL30410 Switching Between Clock Modes 18 System Start-up Sequence FREE-RUN --> HOLDOVER --> NORMAL 18 Single Reference Operation NORMAL --> AUTO HOLDOVER --> NORMAL 19 Single 8 kHz Reference Operation NORMAL --> AUTO HOLDOVER--> HOLDOVER --> NORMAL 20 Dual Reference Operation NORMAL --> AUTO HOLDOVER--> HOLDOVER --> NORMAL. 20 Reference Switching RefSel NORMAL --> HOLDOVER --> NORMAL 21 Power Supply Filtering. 22

Characteristics 23 AC and DC Electrical Characteristics 23 Performance Characteristics 30

Zarlink Semiconductor Inc.

ZL30410

Data Sheet
Ordering Information Box
Change Updated Ordering Information.

ZL30410 Pinout

Pin Connections

IC NC LOCK NC HOLDOVER VDD C34/C44 GND C20i NC VDD RefAlign RefSel C19o GND IC C6o C1.5o PRIOR

SECOR OE NC

RESET NC IC

GND IC

VDD IC NC IC
60 58 56 54 52 50 48 46 44 42 40
62 38
64 36
66 34
68 32

ZL30410
72 28
74 26
76 24
78 22
80 2 4 6 8 10 12 14 16 18 20

NC Tdi Trst Tclk Tms Tdo NC GND C155P C155N VDD AVDD GND IC GND PRI SEC E3/DS3 E3DS3/OC3

IC NC GND NC FCS VDD GND F16o C16o C8o C4o C2o F0o MS1 MS2 F8o

Figure 2 - Pin Connections for 80-pin LQFP package

Zarlink Semiconductor Inc.

Pin Description Pin # 1 2-5 6 7, 8 9

Name IC NC

GND NC FCS

F16o

C16o

ZL30410

Data Sheet

Internal Connection. Leave unconnected.

No internal bonding Connection. Leave unconnected.

Ground. Negative power supply.

No internal bonding Connection. Leave unconnected.

Filter Characteristic Select Input . In Hardware Control, FCS selects the filtering characteristics of the ZL30410. Set this pin high to have a loop filter corner frequency of 6 Hz and limit the phase slope to 41 ns per ms. Set this pin low to have corner frequency of 12 Hz with no phase slope limiting imposed. This pin is internally pulled down to GND.

Positive Power Supply

Ground

Frame Pulse ST-BUS Mbps CMOS tristate output . This is an 8 kHz, 61 ns wide, active low framing pulse, which marks beginning of a ST-BUS frame. This frame pulse is typically used for ST-BUS operation at Mbps.

Clock MHz CMOS tristate output . This clock is used for ST-BUS operation at Mbps.

Clock MHz CMOS tristate output . This clock is used for ST-BUS operation at Mbps.

Clock MHz CMOS tristate output . This clock is used for ST-BUS operation at Mbps.

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Datasheet ID: ZL30410QCG1 649222