ZL30166GDG20040
ZL30166GDG20040 Datasheet
ZL30166
| Part | Datasheet |
|---|---|
ZL30166GDG20040 |
ZL30166GDG20040 (pdf) |
| PDF Datasheet Preview |
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| ZL30166 Triple Clock Translator • Three programmable digital PLLs/Numerically Controlled Oscillators NCOs • Synchronize to any clock rate from 1 KHz to 750 MHz • Four programmable synthesizers generate any clock rate from 1 Hz to 750 MHz with low jitter for 10G PHYs • Flexible two-stage architecture translates between arbitrary data rates, line coding rates and FEC rates • Digital PLLs filter jitter from Hz up to 1 kHz • Automatic hitless reference switching and digital holdover on reference fail • Eight input references configurable as single ended or differential • Any input reference can be fed with sync frame pulse or clock • Programmable DPLLs can synchronize to sync pulse and sync pulse/clock pair Ordering Information ZL30166GDG2 144 Pin LBGA October 2014 Trays Pb Free Tin/Silver/Copper -40oC to +85oC Package Size 13 x 13 mm • Eight LVPECL outputs and eight LVCMOS outputs • Operates from a single crystal resonator or clock oscillator • Field programmable via SPI/I2C interface • OTN muxponders and transponders • 10 Gigabit line cards • Synchronous Ethernet, 10 GBASE-R and 10 GBASE-W • SONET/SDH, Fibre Channel, XAUI Osci Osco Ref0 Ref1 Ref2 Ref3 Ref4 Ref5 Ref6 Ref7 Master Clock Diff / Single Ended Fr0= Br0*Kr0*Mr0/Nr0 Diff / Single Ended Fr1= Br1*Kr1*Mr1/Nr1 Diff / Single Ended Fr2= Br2*Kr2*Mr2/Nr2 Diff / Single Ended Fr3= Br3*Kr3*Mr3/Nr3 Diff / Single Ended Fr4= Br4*Kr4*Mr4/Nr4 Diff / Single Ended Fr5= Br5*Kr5*Mr5/Nr5 Diff / Single Ended Fr6= Br6*Kr6*Mr6/Nr6 Diff / Single Ended Fr7= Br7*Kr7*Mr7/Nr7 ZL30166 DPLL0/NCO0 Select Loop band., Phase slope limit DPLL1/NCO1 Select Loop band., Phase slope limit DPLL2/NCO2 Select Loop band., Phase slope limit State Machine Reference Monitors JTAG Configuration and Status Clock Generator 0 Synthesizer 0 Fs= Bs0*Ks0*16*Ms0/Ns0 Div A Div B Div C Div D Clock Generator 1 Synthesizer 1 Fs= Bs1*Ks1*16*Ms1/Ns1 Div A Div B Div C Div D Clock Generator 2 Synthesizer 2 Fs= Bs2*Ks2*16*Ms2/Ns2 Div A Div B Div C Div D Clock Generator 3 Synthesizer 3 Fs= Bs3*Ks3*16*Ms3/Ns3 Div A Div B Div C Div D LVPECL LVCMOS LVPECL LVCMOS |
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