MT8814AE1

MT8814AE1 Datasheet

ISO-CMOS MT8814 8 x 12 Analog Switch Array

Part	Datasheet
MT8814AE1	MT8814AE1 (pdf)

Related Parts	Information
MT8814AP1	MT8814AP1
MT8814APR1	MT8814APR1

PDF Datasheet Preview
• Internal control latches and address decoder • Short set-up and hold times • Wide operating voltage V to V • 12Vpp analog signal capability • RON 65 max. VDD=12 V, 25C • 10 VDD=12 V, 25C • Full CMOS switch for low distortion • Minimum feedthrough and crosstalk • Separate analog and digital reference supplies • Low power consumption ISO-CMOS technology • Key systems • PBX systems • Mobile radio • Test equipment /instrumentation • Analog/digital multiplexers • Audio/Video switching ISO-CMOS MT8814 8 x 12 Analog Switch Array Data Sheet September 2011 Ordering Information MT8814AE1 40 Pin PDIP* Tubes MT8814AP1 44 Pin PLCC* Tubes MT8814APR1 44 Pin PLCC* Tape & Reel *Pb Free Matte Tin -40C to +85C The Zarlink MT8814 is fabricated in Zarlink’s ISOCMOS technology providing low power dissipation and high reliability. The device contains a 8 x 12 array of crosspoint switches along with a 7 to 96 line decoder and latch circuits. Any one of the 96 switches can be addressed by selecting the appropriate seven address bits. The selected switch can be turned on or off by applying a logical one or zero to the DATA input. VSS is the ground reference of the digital inputs. The range of the analog signal is from VDD to VEE. Chip Select CS allows the crosspoint array to be cascaded for matrix expansion. CS STROBE DATA RESET VDD VEE 7 to 96 Decoder Latches 8 x 12 Switch Array Xi I/O i=0-11 Yi I/O i=0-7 Figure 1 - Functional Block Diagram Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 1997-2011, Zarlink Semiconductor Inc. All Rights Reserved. MT8814 Change Summary Changes from the May 2005 issue to the September 2011 issue. Data Sheet Item Ordering Information Change Removed leaded packages as per PCN notice. NC AX3 RESET AY2 Y3 VDD Y2 DATA Y1 CS Y3 1 AY2 2 RESET 3 AX3 4 AX0 5 NC 6 NC 7 X6 8 X7 9 X8 10 X9 11 X10 12 X11 13 NC 14 Y7 15 VSS 16 Y6 17 STROBE 18 Y5 19 VSS 20 40 VDD 39 Y2 38 DATA 37 Y1 36 CS 35 Y0 34 NC 33 X0 32 X1 31 X2 30 X3 29 X4 28 X5 27 NC 26 NC 25 AY1 24 AY0 23 AX2 22 AX1 21 Y4 AX0 NC X7 X8 X9 X10 X11 NC Y7 VSS 6 5 4 3 2 1 44 43 42 41 40 39 Y0 38 NC 37 X0 36 X1 35 X2 34 X3 33 X4 32 X5 31 NC 30 NC 29 NC 18 19 20 21 22 23 24 25 26 27 28 NC Y6 STROBE Y5 VEE Y4 AX1 AX2 AY0 AY1 NC 40 PIN PLASTIC DIP Figure 2 - Pin Connections 44 PIN PLCC Pin Description Pin # PDIP 1 PLCC 1 4,5 6,7 8-13 4,7 5,6,8 9-14 15,18 Name Y3 Analog Input/Output this is connected to the Y3 column of the switch array. AY2 Y2 Address Line Input . RESET Master RESET Input this is used to turn off all switches regardless of the condition of CS. Active High. AX3,AX0 X3 and X0 Address Lines Inputs . NC No Connection. X6-X11 X6-X11 Analog Inputs/Outputs these are connected to the X6-X11 rows of the switch array.

PDF Datasheet Preview

• Internal control latches and address decoder
• Short set-up and hold times
• Wide operating voltage V to V
• 12Vpp analog signal capability
• RON 65 max. VDD=12 V, 25C
• 10 VDD=12 V, 25C
• Full CMOS switch for low distortion
• Minimum feedthrough and crosstalk
• Separate analog and digital reference supplies
• Low power consumption ISO-CMOS technology
• Key systems
• PBX systems
• Mobile radio
• Test equipment /instrumentation
• Analog/digital multiplexers
• Audio/Video switching

ISO-CMOS MT8814 8 x 12 Analog Switch Array

Data Sheet

September 2011
Ordering Information

MT8814AE1 40 Pin PDIP* Tubes MT8814AP1 44 Pin PLCC* Tubes MT8814APR1 44 Pin PLCC* Tape & Reel
*Pb Free Matte Tin -40C to +85C

The Zarlink MT8814 is fabricated in Zarlink’s ISOCMOS technology providing low power dissipation and high reliability. The device contains a 8 x 12 array of crosspoint switches along with a 7 to 96 line decoder and latch circuits. Any one of the 96 switches can be addressed by selecting the appropriate seven address bits. The selected switch can be turned on or off by applying a logical one or zero to the DATA input. VSS is the ground reference of the digital inputs. The range of the analog signal is from VDD to VEE. Chip Select CS allows the crosspoint array to be cascaded for matrix expansion.

CS STROBE

DATA RESET

VDD VEE
7 to 96 Decoder

Latches
8 x 12 Switch Array

Xi I/O i=0-11

Yi I/O i=0-7

Figure 1 - Functional Block Diagram

Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

Copyright 1997-2011, Zarlink Semiconductor Inc. All Rights Reserved.

MT8814

Change Summary

Changes from the May 2005 issue to the September 2011 issue.

Data Sheet
Item Ordering Information

Change Removed leaded packages as per PCN notice.

NC AX3 RESET AY2 Y3 VDD Y2 DATA Y1 CS

Y3 1 AY2 2 RESET 3 AX3 4 AX0 5 NC 6 NC 7

X6 8 X7 9 X8 10 X9 11 X10 12 X11 13 NC 14 Y7 15 VSS 16 Y6 17 STROBE 18

Y5 19 VSS 20
40 VDD 39 Y2 38 DATA 37 Y1 36 CS 35 Y0 34 NC 33 X0 32 X1 31 X2 30 X3 29 X4 28 X5 27 NC 26 NC 25 AY1 24 AY0 23 AX2
22 AX1 21 Y4

AX0 NC

X7 X8 X9 X10

X11 NC Y7 VSS
6 5 4 3 2 1 44 43 42 41 40
39 Y0
38 NC
37 X0
36 X1
35 X2
34 X3
33 X4
32 X5
31 NC
30 NC
29 NC
18 19 20 21 22 23 24 25 26 27 28

NC Y6 STROBE Y5 VEE Y4 AX1 AX2 AY0 AY1 NC
40 PIN PLASTIC DIP

Figure 2 - Pin Connections
44 PIN PLCC

Pin Description

Pin #

PDIP 1

PLCC 1
4,5 6,7 8-13
4,7 5,6,8 9-14
15,18

Name

Y3 Analog Input/Output this is connected to the Y3 column of the switch array.

AY2 Y2 Address Line Input . RESET Master RESET Input this is used to turn off all switches regardless of the
condition of CS. Active High. AX3,AX0 X3 and X0 Address Lines Inputs .

NC No Connection.

X6-X11 X6-X11 Analog Inputs/Outputs these are connected to the X6-X11 rows of the switch array.

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Datasheet ID: MT8814AE1 649081