MAX3610AU/D

MAX3610AU/D Datasheet

MAX3610

Part	Datasheet
MAX3610AU/D	MAX3610AU/D (pdf)

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MAX3610 EVALUATION KIT AVAILABLE Low-Jitter 106.25MHz/212.5MHz Fibre-Channel Clock Generator The MAX3610 is a low-jitter, high-performance, dual-rate clock generator optimized for 1Gbps/2Gbps/4Gbps Fibre-Channel applications. When connected with an external AT-cut crystal, the device generates a precision clock output by integrating a crystal oscillator with Maxim’s low-noise phase-locked loop PLL providing a low-cost solution. By coupling Maxim’s low-noise PLL design featuring a low-jitter generation VCO with an inexpensive fundamental mode crystal, the MAX3610 provides the optimum combination of low cost, flexibility, and high performance. The MAX3610 output frequency is selectable. When using a 26.5625MHz crystal, the output clock rate can be set to either 106.25MHz or 212.5MHz. When operating at 106.25MHz, the typical phase jitter is 0.7psRMS from 12kHz to 20MHz. The MAX3610A has low-voltage positive-emitter-coupled logic LVPECL clock output drivers. The MAX3610B has low-voltage differential-signal LVDS clock output drivers. The MAX3610 output drivers can also be disabled. The MAX3610 operates from a single +3.3V supply. The PECL version typically consumes 165mW, while the LVDS version typically consumes 174mW. Both devices are available in die form and have a 0°C to +85°C operating temperature range. Fibre-Channel Hard Disk Drives Host Bus Adapters Raid Controllers Fibre-Channel Switches Clock Output Frequencies 106.25MHz or 212.5MHz Phase Jitter 0.7psRMS LVPECL or LVDS Output Excellent Power-Supply Noise Rejection Supply Current 50mA at +3.3V Supply LVPECL 53mA at +3.3V Supply LVDS 0°C to +85°C Temperature Range Optional Output Disable Ordering Information PART TEMP RANGE PINPACKAGE OUTPUTS MAX3610AU/D 0°C to +85°C Die MAX3610BU/D 0°C to +85°C Die LVPECL LVDS Dice are designed to operate from 0°C to +85°C, but are tested and guaranteed only at TA = +25°C. Typical Operating Circuits +3.3V +3.3V 0.1µF 0.1µF AT CUT CRYSTAL OE VCC FREQSET +3.3V MAX3610A OUT+ OUT- DEVICE WITH LVPECL INPUTS LVPECL OUTPUTS VCC -2V OPERATING AT 106.25MHz AT CUT CRYSTAL OE VCC FREQSET +3.3V MAX3610B OUT+ OUT- DEVICE WITH LVDS INPUTS GND LVDS OUTPUTS OPERATING AT 106.25MHz MAX3610 Low-Jitter 106.25MHz/212.5MHz Fibre-Channel Clock Generator ABSOLUTE MAXIMUM RATINGS Supply Voltage to +5.0V Voltage at FREQSET, OE............................-0.5V to VCC + 0.5V Voltage at X1 to +0.8V Voltage at X2 to 2V PECL Output Current LVDS Output Voltage .................................-0.5V to VCC + 0.5V Operating Temperature Range...............................0°C to +85°C Storage Temperature Range .............................-65°C to +160°C Processing Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS VCC = +3.0V to +3.6V, TA = 0°C to +85°C. Typical values are at VCC = +3.3V and TA = +25°C, unless otherwise noted. Note 1 PARAMETER CONDITIONS Optimal performance is achieved by integrating the crystal oscillator with a low-noise PLL. The PLL consists of a digital phase/frequency detector PFD and low-jitter generation VCO. The VCO signal is scaled by clockdivider circuitry and applied to the output buffer. The MAX3610 is available with either LVPECL or LVDS output buffers see the Ordering Information . Oscillator Gain Circuit The input capacitance of the oscillator gain circuit is trimmed to 12pF of capacitance and produces oscillations at 26.5625MHz when interfaced with the appropriate external crystal see Table 1 for the external crystal specifications . PLL The PLL generates a 1.7GHz high-speed clock signal based on the 26.5625MHz crystal oscillator output. Clock-divider circuit M generates the output clock by scaling the VCO output frequency. Clock-divider circuit N applies a scaled version of the output clock signal to the PFD. A TTL low applied to FREQSET, sets clockdivider M ratio to 16, and clock-divider N ratio to With FREQSET pulled low, the output clock rate is 212.5MHz. A TTL high applied to FREQSET sets the clock-divider M ratio to 32, and clock-divider N ratio to With FREQSET pulled high, the output clock rate is 106.25MHz. Output Drivers The MAX3610 is available with either LVPECL MAX3610A or LVDS MAX3610B output buffers. When not needed, the output buffers can be disabled. When disabled, the LVPECL output buffer goes to a high-impedance state. However, the LVDS outputs go to a differential 1 OUT+ latched high and OUT- latched low when the outputs are disabled. Design Procedure Crystal Resonator Specifications The MAX3610 is designed to operate with an inexpensive fundamental mode crystal. Table 1 specifies the characteristics of a typical crystal to be interfaced with the MAX3610. MAX3610 Low-Jitter 106.25MHz/212.5MHz Fibre-Channel Clock Generator Table Crystal Resonator Specifications PARAMETER VALUE Crystal Fundamental AT-cut Nominal Oscillator Frequency 26.5625MHz Shunt Capacitance Co Co/Cs Load Capacitance Note 6 12pF Equivalent Series Resistance ESR to Maximum Crystal Drive Level 500µW Note 6 The load capacitance includes the oscillation-circuit input capacitance, as well as the parasitic capacitance caused from the assembling/packaging of the blank crystal and IC. Figure Equivalent Crystal Resonator Circuit Model Applications Information Figure LVPECL Output Stage OUT+ ESD STRUCTURES OUT- Figure LVDS Output Stage OUT+ OUT- ESD STRUCTURES MAX3610 Low-Jitter 106.25MHz/212.5MHz Fibre-Channel Clock Generator Table Bond Pad Coordinates BP1 BP2 BP3 BP4 BP5 BP6 BP7 BP8 BP9 BP10 BP11 BP12 BP13 BP14 BP15 BP16 BP17 BP18 BP19 BP20 Index pad NAME N.C. N.C. N.C. X1 X2 N.C. N.C. OE N.C. N.C. N.C. OUTGND OUT+ N.C. N.C. N.C. N.C. FREQSET VCC COORDINATES

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MAX3610

EVALUATION KIT AVAILABLE

Low-Jitter 106.25MHz/212.5MHz Fibre-Channel Clock Generator

The MAX3610 is a low-jitter, high-performance, dual-rate clock generator optimized for 1Gbps/2Gbps/4Gbps Fibre-Channel applications. When connected with an external AT-cut crystal, the device generates a precision clock output by integrating a crystal oscillator with Maxim’s low-noise phase-locked loop PLL providing a low-cost solution. By coupling Maxim’s low-noise PLL design featuring a low-jitter generation VCO with an inexpensive fundamental mode crystal, the MAX3610 provides the optimum combination of low cost, flexibility, and high performance.

The MAX3610 output frequency is selectable. When using a 26.5625MHz crystal, the output clock rate can be set to either 106.25MHz or 212.5MHz. When operating at 106.25MHz, the typical phase jitter is 0.7psRMS from 12kHz to 20MHz. The MAX3610A has low-voltage positive-emitter-coupled logic LVPECL clock output drivers. The MAX3610B has low-voltage differential-signal LVDS clock output drivers. The MAX3610 output drivers can also be disabled.

The MAX3610 operates from a single +3.3V supply. The PECL version typically consumes 165mW, while the LVDS version typically consumes 174mW. Both devices are available in die form and have a 0°C to +85°C operating temperature range.

Fibre-Channel Hard Disk Drives

Host Bus Adapters

Raid Controllers

Fibre-Channel Switches

Clock Output Frequencies 106.25MHz or 212.5MHz

Phase Jitter 0.7psRMS LVPECL or LVDS Output Excellent Power-Supply Noise Rejection Supply Current 50mA at +3.3V Supply LVPECL
53mA at +3.3V Supply LVDS 0°C to +85°C Temperature Range Optional Output Disable
Ordering Information

PART

TEMP RANGE

PINPACKAGE

OUTPUTS

MAX3610AU/D 0°C to +85°C Die MAX3610BU/D 0°C to +85°C Die

LVPECL LVDS

Dice are designed to operate from 0°C to +85°C, but are tested and guaranteed only at TA = +25°C.

Typical Operating Circuits
+3.3V
+3.3V
0.1µF
0.1µF

AT CUT CRYSTAL

OE VCC FREQSET
+3.3V

MAX3610A

OUT+

OUT-

DEVICE WITH LVPECL INPUTS

LVPECL OUTPUTS

VCC -2V OPERATING AT 106.25MHz

AT CUT CRYSTAL

OE VCC FREQSET
+3.3V

MAX3610B

OUT+

OUT-

DEVICE WITH LVDS INPUTS

GND LVDS OUTPUTS

OPERATING AT 106.25MHz

MAX3610

Low-Jitter 106.25MHz/212.5MHz Fibre-Channel Clock Generator

ABSOLUTE MAXIMUM RATINGS

Supply Voltage to +5.0V Voltage at FREQSET, OE............................-0.5V to VCC + 0.5V Voltage at X1 to +0.8V Voltage at X2 to 2V PECL Output Current

LVDS Output Voltage .................................-0.5V to VCC + 0.5V Operating Temperature Range...............................0°C to +85°C Storage Temperature Range .............................-65°C to +160°C Processing

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

VCC = +3.0V to +3.6V, TA = 0°C to +85°C. Typical values are at VCC = +3.3V and TA = +25°C, unless otherwise noted. Note 1

PARAMETER

CONDITIONS
Optimal performance is achieved by integrating the crystal oscillator with a low-noise PLL. The PLL consists of a digital phase/frequency detector PFD and low-jitter generation VCO. The VCO signal is scaled by clockdivider circuitry and applied to the output buffer. The MAX3610 is available with either LVPECL or LVDS output buffers see the Ordering Information .

Oscillator Gain Circuit The input capacitance of the oscillator gain circuit is trimmed to 12pF of capacitance and produces oscillations at 26.5625MHz when interfaced with the appropriate external crystal see Table 1 for the external crystal specifications .

PLL The PLL generates a 1.7GHz high-speed clock signal based on the 26.5625MHz crystal oscillator output. Clock-divider circuit M generates the output clock by
scaling the VCO output frequency. Clock-divider circuit N applies a scaled version of the output clock signal to the PFD. A TTL low applied to FREQSET, sets clockdivider M ratio to 16, and clock-divider N ratio to With FREQSET pulled low, the output clock rate is 212.5MHz. A TTL high applied to FREQSET sets the clock-divider M ratio to 32, and clock-divider N ratio to With FREQSET pulled high, the output clock rate is 106.25MHz.

Output Drivers The MAX3610 is available with either LVPECL MAX3610A or LVDS MAX3610B output buffers. When not needed, the output buffers can be disabled. When disabled, the LVPECL output buffer goes to a high-impedance state. However, the LVDS outputs go to a differential 1 OUT+ latched high and OUT- latched low when the outputs are disabled.

Design Procedure

Crystal Resonator Specifications The MAX3610 is designed to operate with an inexpensive fundamental mode crystal. Table 1 specifies the characteristics of a typical crystal to be interfaced with the MAX3610.

MAX3610

Low-Jitter 106.25MHz/212.5MHz Fibre-Channel Clock Generator

Table Crystal Resonator Specifications

PARAMETER

VALUE

Crystal

Fundamental AT-cut

Nominal Oscillator Frequency
26.5625MHz

Shunt Capacitance Co

Co/Cs

Load Capacitance Note 6
12pF

Equivalent Series Resistance ESR to

Maximum Crystal Drive Level
500µW

Note 6 The load capacitance includes the oscillation-circuit input capacitance, as well as the parasitic capacitance caused from the assembling/packaging of the blank crystal and IC.

Figure Equivalent Crystal Resonator Circuit Model

Applications Information

Figure LVPECL Output Stage

OUT+

ESD STRUCTURES

OUT-

Figure LVDS Output Stage

OUT+

OUT-

ESD STRUCTURES

MAX3610

Low-Jitter 106.25MHz/212.5MHz Fibre-Channel Clock Generator

Table Bond Pad Coordinates

BP1 BP2 BP3 BP4 BP5 BP6 BP7 BP8 *BP9 BP10 BP11 BP12 BP13 BP14 BP15 BP16 BP17 BP18 BP19 BP20 *Index pad

NAME

N.C. N.C. N.C. X1 X2 N.C. N.C. OE N.C. N.C. N.C. OUTGND OUT+ N.C. N.C. N.C. N.C. FREQSET VCC

COORDINATES

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Datasheet ID: MAX3610AU/D 649052