LE58QL063HVC

LE58QL063HVC Datasheet

Le58QL061/063

Part	Datasheet
LE58QL063HVC	LE58QL063HVC (pdf)

Related Parts	Information
LE58QL061BVCT	LE58QL061BVCT
LE58QL063HVCT	LE58QL063HVCT
LE58QL061BVC	LE58QL061BVC

PDF Datasheet Preview
Le58QL061/063 Quad Low Voltage Subcriber Line Audio-Processing Circuit - Ve580 Series Data Sheet • Low-power, V CMOS technology with 5 V tolerant digital inputs • Pin programmable PCM/MPI or GCI interface • Software and coefficient compatible to the Le79Q061/063 QSLAC device • Standard PCM/microprocessor interface PCM/MPI mode • Single or Dual PCM ports available • Time slot assigner up to 128 channels per port • Clock slot and transmit clock edge options • Optional supervision on the PCM highway • or MHz master clock derived from MCLK or PCLK • µP access to PCM data • Real Time Data with interrupt open drain or TTL • Broadcast mode • General Circuit Interface GCI mode • Control and PCM data on a single port • Mbits/s data rate • MHz or MHz clock option • Performs the functions of four codec/filters • Software programmable: • SLIC device input impedance and Transhybrid balance • Transmit and receive gains and Equalization • Programmable Digital I/O pins with debouncing • A-law, µ-law, or linear coding • Built-in test modes with loopback, tone generation, and µP access to PCM data • Mixed state analog and digital impedance scaling • Performance guaranteed over a 12 dB gain range • Supports multiplexed SLIC device outputs Document ID# 080754 Version 8 June 2011 Ordering Information Device Package1 Green Packing2 Le58QL061BVC Le58QL063HVC 44-pin TQFP 64-pin LQFP Trays The green package meets RoHS Directive 2002/95/EC of the European Council to minimize the environmental impact of electrical equipment. For delivery using a tape and reel packing system, add a "T" suffix to the OPN Ordering Part Number when placing an order. • 256 kHz or 293 kHz chopper clock for Zarlink SLIC devices with switching regulator • Maximum channel bandwidth for V.90 modems • Codec function on telephone switch line cards Analog VIN 1 VOUT 1 VIN 2 VOUT 2 VIN 3 VOUT 3 VIN 4 VOUT 4 VREF SLIC CD11 CD21 C31 C41 C51 C61 C71 CD12 CD22 C32 C42 C52 C62 C72 CD13 CD23 C33 C43 C53 C63 C73 CD14 CD24 C34 C44 C54 C64 C74 CHCLK Signal Processing Channel 1 CH 1 Signal Processing Channel 2 CH 2 Signal Processing Channel 3 CH 3 Signal Processing Channel 4 CH 4 PMC & GCI Interface & Time Slot Assigner TSA Clock & Reference Circuits GCI/PCM Interface DXA/DU DRA/DD TSCA DXB DRB TSCB FS/FSC PCLK/DCL MCLK/E1 SLIC Interface GCI Control Logic & Microprocessor Interface DCLK/S0 CS/PG DIO/S1 INT RST Figure 1 - Block Diagram Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2009-2011, Zarlink Semiconductor Inc. All Rights Reserved. Le58QL061/063 Data Sheet The Le58QL061/063 Quad Low Voltage Subscriber Line Audio-Processing Circuit QLSLAC devices integrate the key functions of analog line cards into high-performance, very-programmable, four-channel codec-filter devices. The QLSLAC devices are based on the proven design of Zarlink’s reliable SLAC device families. The advanced architecture of the QLSLAC devices implements four independent channels and employs digital filters to allow software control of transmission, thus providing a cost-effective solution for the audio-processing function of programmable line cards. The QLSLAC devices are software and coefficient compatible to the QSLAC devices. Advanced submicron CMOS technology makes the Le58QL061/063 QLSLAC devices economical, with both the functionality and the low power consumption needed in line card designs to maximize line card density at minimum cost. When used with four Zarlink SLIC devices, a QLSLAC device provides a complete software-configurable solution to the BORSCHT functions. The Le58QL061/063 device supports the feature set of the Le58QL02/021/031 device and provides a General Circuit Interface as a programmable mode. Ordering Information “GCI Timing Specifications“ Description Obsoleted Le58QL061FJC package. Corrected tsD Data Setup Min. to Zarlink Semiconductor Inc. Le58QL061/063 Data Sheet Table of Contents Product Description. 8 Block Descriptions 8 Clock and Reference Circuits 8 Microprocessor Interface MPI 9 Time Slot Assigner TSA 9 Signal Processing Channels CHx 9 SLIC Device Interface SLI . 9 Connection Diagrams 9 Pin Descriptions. 11 Absolute Maximum Ratings 14 Package Assembly 14 Operating Ranges 15 Environmental Ranges 15 Electrical Ranges. 15 Electrical Characteristics 16 Transmission Characteristics 18 Attenuation Distortion 19 Group Delay Distortion 20 Gain Linearity 21 Total Distortion Including Quantizing Distortion. 22 Discrimination Against Out-of-Band Input Signals. 22 Discrimination Against 12- and 16-kHz Metering Signals 23 Spurious Out-of-Band Signals at the Analog Output 23 Overload Compression 24 Switching Characteristics 25 Switching Waveforms 28 GCI Timing Specifications 32 GCI Waveforms 33 OPERATING THE QLSLAC DEVICE 35 Power-Up Sequence 35 PCM and GCI State Selection 35 Channel Enable EC Register PCM/MPI Mode 36 SLIC Device Control and Data Lines. 36 Clock Mode Operation. 36 E1 Multiplex Operation 38 Debounce Filters Operation. 40 Real-Time Data Register Operation 42 Interrupt 42 Interrupt Mask Register 42 Active State 42 Inactive State. 42 Chopper Clock. 43 Reset States 43 Signal Processing 44 Overview of Digital Filters 44 Two-Wire Impedance Matching. 44 Frequency Response Correction and Equalization 44 Transhybrid Balancing. 45 Gain Adjustment 45 Transmit Signal Processing. 45 Transmit PCM Interface PCM/MPI Mode 45 Zarlink Semiconductor Inc. Le58QL061/063 Data Sheet Table of Contents Data Upstream Interface GCI Mode 46 Receive Signal Processing 46 Receive PCM Interface PCM/MPI Mode . 46 Data Downstream Interface GCI Mode 47 Analog Impedance Scaling Network AISN 47 Speech Coding 48 Double PCLK DPCK Operation PCM/MPI Mode 48 Signaling on the PCM Highway PCM/MPI Mode 48 Robbed-Bit Signaling Compatibility PCM/MPI Mode 48 Default Filter Coefficients 50 Command Description and Formats 50 Command Field Summary. 50 Microprocessor Interface Description 53 Summary of MPI Commands 54 General Circuit Interface GCI Specifications 72 GCI General Description 72 GCI Format and Command Structure 73 Signaling and Control SC Channel 74 Monitor Channel 76 Programming with the Monitor Channel 79 Channel Identification Command CIC . 80 Zarlink Semiconductor Inc. Le58QL061/063 Data Sheet Table of Contents General Structure of Other Commands. 81 Summary of Monitor Channel Commands GCI Commands 82 TOP Transfer Operation Command 83 SOP Status Operation Command 83 SOP Control Byte Command Format 84 COP Coefficient Operation Command 90 Details of COP, CSD Data Commands 91 Programmable Filters 98 User Test States and Operating Conditions 100 A-Law and µ-Law Companding 100 APPLICATIONS 103 Application Circuit 104 Line Card Parts List 105 Physical Dimensions 106 44-Pin TQFP 106 Zarlink Semiconductor Inc. Le58QL061/063 Data Sheet List of Figures Figure 1 - Block Diagram 1 Figure 2 - Transmit Path Attenuation vs. Frequency 19 Figure 3 - Receive Path Attenuation vs. Frequency 20 Figure 4 - Group Delay Distortion 20 Figure 5 - A-law Gain Linearity with Tone Input Both Paths 21 Figure 6 - µ-law Gain Linearity with Tone Input Both Paths . 21 Figure 7 - Total Distortion with Tone Input Both Paths . 22 Figure 8 - Discrimination Against Out-of-Band Signals 23 Figure 9 - Spurious Out-of-Band Signals 24 Figure 10 - Analog-to-Analog Overload Compression 24 Figure 11 - Input and Output Waveforms for AC Tests. 28 Figure 12 - Microprocessor Interface Input Mode 28 Figure 13 - Microprocessor Interface Output Mode 29 Figure 14 - PCM Highway Timing for XE = 0 Transmit on Negative PCLK Edge 29 Figure 15 - PCM Highway Timing for XE = 1 Transmit on Positive PCLK Edge 30 Figure 16 - Double PCLK PCM Timing 31 Figure 17 - Master Clock Timing 32 Figure 18 - MHz DCL Operation 33 Figure 19 - MHz DCL Operation 34 Figure 20 - Clock Mode Options PCM/MPI Mode 37 Figure 21 - SLIC Device I/O, E1 Multiplex and Real-Time Data Register Operation 39 Figure 22 - E1 Multiplex Internal Timing 40 Figure 23 - MPI Real-Time Data Register 41 Figure 24 - QLSLAC Device Transmission Block Diagram 44 Figure 25 - Robbed-Bit Frame 49 Figure 26 - Time Slot Control and GCI Interface 73 Figure 27 - Multiplexed GCI Time Slot Structure 74 Figure 28 - Security Procedure for C/I Downstream Bytes 75 Figure 29 - Maximum Speed Monitor Handshake Timing 77 Figure 30 - Monitor Transmitter Mode Diagram 78 Figure 31 - Monitor Receiver State Diagram 79 Figure 32 - Le7920 SLIC/QLSLAC Device Application Circuit. 104 Zarlink Semiconductor Inc. Le58QL061/063 Data Sheet List of Tables Table 1 - QLSLAC Device Features 8 Table 2 - 0 dBm0 Voltage Definitions with Unity Gain in X, R, GX, GR, AX and AR 18 Table 3 - PCM/GCI Mode Selection 35 Table 4 - Channel Parameters 50 Table 5 - Channel Monitors 52 Table 6 - Global Chip Parameters 52 Table 7 - Global Chip Status Monitors 52 Table 8 - GCI Channel Assignment Codes 72 Table 9 - Generic Byte Transmission Sequence 80 Table 10 - Byte Transmission Sequence for TOP Command. 83 Table 11 - General Transmission Sequence of SOP Command 83 Table 12 - Generic Transmission Sequence for COP Command. 90 Table 13 - A-Law Positive Input Values. 101 Table 14 - µ-Law Positive Input Values 102

PDF Datasheet Preview

Le58QL061/063

Quad Low Voltage Subcriber Line Audio-Processing Circuit - Ve580 Series

Data Sheet
• Low-power, V CMOS technology with 5 V tolerant digital inputs
• Pin programmable PCM/MPI or GCI interface
• Software and coefficient compatible to the

Le79Q061/063 QSLAC device
• Standard PCM/microprocessor interface

PCM/MPI mode
• Single or Dual PCM ports available
• Time slot assigner up to 128 channels per port
• Clock slot and transmit clock edge options
• Optional supervision on the PCM highway
• or MHz master clock derived from MCLK or PCLK
• µP access to PCM data
• Real Time Data with interrupt open drain or TTL
• Broadcast mode
• General Circuit Interface GCI mode
• Control and PCM data on a single port
• Mbits/s data rate
• MHz or MHz clock option
• Performs the functions of four codec/filters
• Software programmable:
• SLIC device input impedance and Transhybrid balance
• Transmit and receive gains and Equalization
• Programmable Digital I/O pins with debouncing
• A-law, µ-law, or linear coding
• Built-in test modes with loopback, tone
generation, and µP access to PCM data
• Mixed state analog and digital impedance
scaling
• Performance guaranteed over a 12 dB gain range
• Supports multiplexed SLIC device outputs

Document ID# 080754

Version 8

June 2011
Ordering Information

Device

Package1 Green Packing2

Le58QL061BVC Le58QL063HVC
44-pin TQFP 64-pin LQFP

Trays

The green package meets RoHS Directive 2002/95/EC of the European Council to minimize the environmental impact of electrical equipment.
For delivery using a tape and reel packing system, add a "T" suffix to the OPN Ordering Part Number when placing an order.
• 256 kHz or 293 kHz chopper clock for Zarlink SLIC devices with switching regulator
• Maximum channel bandwidth for V.90 modems
• Codec function on telephone switch line cards

Analog

VIN 1 VOUT 1

VIN 2 VOUT 2

VIN 3 VOUT 3

VIN 4 VOUT 4

VREF

SLIC

CD11 CD21

C31 C41 C51 C61 C71

CD12 CD22

C32 C42 C52 C62 C72

CD13 CD23

C33 C43 C53 C63 C73

CD14 CD24

C34 C44 C54 C64 C74 CHCLK

Signal Processing Channel 1 CH 1

Signal Processing Channel 2 CH 2

Signal Processing Channel 3 CH 3

Signal Processing Channel 4 CH 4

PMC & GCI Interface &

Time Slot Assigner TSA

Clock &

Reference Circuits

GCI/PCM Interface DXA/DU DRA/DD TSCA DXB DRB TSCB

FS/FSC PCLK/DCL MCLK/E1

SLIC Interface

GCI Control Logic & Microprocessor Interface

DCLK/S0 CS/PG DIO/S1

INT RST

Figure 1 - Block Diagram

Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

Copyright 2009-2011, Zarlink Semiconductor Inc. All Rights Reserved.

Le58QL061/063

Data Sheet

The Le58QL061/063 Quad Low Voltage Subscriber Line Audio-Processing Circuit QLSLAC devices integrate the key functions of analog line cards into high-performance, very-programmable, four-channel codec-filter devices. The QLSLAC devices are based on the proven design of Zarlink’s reliable SLAC device families. The advanced architecture of the QLSLAC devices implements four independent channels and employs digital filters to allow software control of transmission, thus providing a cost-effective solution for the audio-processing function of programmable line cards. The QLSLAC devices are software and coefficient compatible to the QSLAC devices.

Advanced submicron CMOS technology makes the Le58QL061/063 QLSLAC devices economical, with both the functionality and the low power consumption needed in line card designs to maximize line card density at minimum cost. When used with four Zarlink SLIC devices, a QLSLAC device provides a complete software-configurable solution to the BORSCHT functions.

The Le58QL061/063 device supports the feature set of the Le58QL02/021/031 device and provides a General Circuit Interface as a programmable mode.
Ordering Information “GCI Timing Specifications“

Description Obsoleted Le58QL061FJC package. Corrected tsD Data Setup Min. to

Zarlink Semiconductor Inc.

Le58QL061/063

Data Sheet

Table of Contents

Product Description. 8

Block Descriptions 8 Clock and Reference Circuits 8 Microprocessor Interface MPI 9 Time Slot Assigner TSA 9 Signal Processing Channels CHx 9 SLIC Device Interface SLI . 9

Connection Diagrams 9

Pin Descriptions. 11

Absolute Maximum Ratings 14 Package Assembly 14

Operating Ranges 15 Environmental Ranges 15 Electrical Ranges. 15

Electrical Characteristics 16 Transmission Characteristics 18 Attenuation Distortion 19 Group Delay Distortion 20 Gain Linearity 21 Total Distortion Including Quantizing Distortion. 22 Discrimination Against Out-of-Band Input Signals. 22 Discrimination Against 12- and 16-kHz Metering Signals 23 Spurious Out-of-Band Signals at the Analog Output 23 Overload Compression 24

Switching Characteristics 25

Switching Waveforms 28 GCI Timing Specifications 32 GCI Waveforms 33

OPERATING THE QLSLAC DEVICE 35 Power-Up Sequence 35 PCM and GCI State Selection 35 Channel Enable EC Register PCM/MPI Mode 36 SLIC Device Control and Data Lines. 36 Clock Mode Operation. 36 E1 Multiplex Operation 38 Debounce Filters Operation. 40 Real-Time Data Register Operation 42 Interrupt 42 Interrupt Mask Register 42 Active State 42 Inactive State. 42 Chopper Clock. 43 Reset States 43

Signal Processing 44 Overview of Digital Filters 44 Two-Wire Impedance Matching. 44 Frequency Response Correction and Equalization 44 Transhybrid Balancing. 45 Gain Adjustment 45 Transmit Signal Processing. 45 Transmit PCM Interface PCM/MPI Mode 45

Zarlink Semiconductor Inc.

Le58QL061/063

Data Sheet

Table of Contents

Data Upstream Interface GCI Mode 46 Receive Signal Processing 46 Receive PCM Interface PCM/MPI Mode . 46 Data Downstream Interface GCI Mode 47 Analog Impedance Scaling Network AISN 47 Speech Coding 48 Double PCLK DPCK Operation PCM/MPI Mode 48 Signaling on the PCM Highway PCM/MPI Mode 48 Robbed-Bit Signaling Compatibility PCM/MPI Mode 48 Default Filter Coefficients 50

Command Description and Formats 50 Command Field Summary. 50 Microprocessor Interface Description 53

Summary of MPI Commands 54

General Circuit Interface GCI Specifications 72 GCI General Description 72 GCI Format and Command Structure 73 Signaling and Control SC Channel 74 Monitor Channel 76 Programming with the Monitor Channel 79 Channel Identification Command CIC . 80

Zarlink Semiconductor Inc.

Le58QL061/063

Data Sheet

Table of Contents

General Structure of Other Commands. 81 Summary of Monitor Channel Commands GCI Commands 82

TOP Transfer Operation Command 83 SOP Status Operation Command 83 SOP Control Byte Command Format 84 COP Coefficient Operation Command 90 Details of COP, CSD Data Commands 91 Programmable Filters 98 User Test States and Operating Conditions 100 A-Law and µ-Law Companding 100 APPLICATIONS 103 Application Circuit 104 Line Card Parts List 105 Physical Dimensions 106 44-Pin TQFP 106

Zarlink Semiconductor Inc.

Le58QL061/063

Data Sheet

List of Figures

Figure 1 - Block Diagram 1 Figure 2 - Transmit Path Attenuation vs. Frequency 19 Figure 3 - Receive Path Attenuation vs. Frequency 20 Figure 4 - Group Delay Distortion 20 Figure 5 - A-law Gain Linearity with Tone Input Both Paths 21 Figure 6 - µ-law Gain Linearity with Tone Input Both Paths . 21 Figure 7 - Total Distortion with Tone Input Both Paths . 22 Figure 8 - Discrimination Against Out-of-Band Signals 23 Figure 9 - Spurious Out-of-Band Signals 24 Figure 10 - Analog-to-Analog Overload Compression 24 Figure 11 - Input and Output Waveforms for AC Tests. 28 Figure 12 - Microprocessor Interface Input Mode 28 Figure 13 - Microprocessor Interface Output Mode 29 Figure 14 - PCM Highway Timing for XE = 0 Transmit on Negative PCLK Edge 29 Figure 15 - PCM Highway Timing for XE = 1 Transmit on Positive PCLK Edge 30 Figure 16 - Double PCLK PCM Timing 31 Figure 17 - Master Clock Timing 32 Figure 18 - MHz DCL Operation 33 Figure 19 - MHz DCL Operation 34 Figure 20 - Clock Mode Options PCM/MPI Mode 37 Figure 21 - SLIC Device I/O, E1 Multiplex and Real-Time Data Register Operation 39 Figure 22 - E1 Multiplex Internal Timing 40 Figure 23 - MPI Real-Time Data Register 41 Figure 24 - QLSLAC Device Transmission Block Diagram 44 Figure 25 - Robbed-Bit Frame 49 Figure 26 - Time Slot Control and GCI Interface 73 Figure 27 - Multiplexed GCI Time Slot Structure 74 Figure 28 - Security Procedure for C/I Downstream Bytes 75 Figure 29 - Maximum Speed Monitor Handshake Timing 77 Figure 30 - Monitor Transmitter Mode Diagram 78 Figure 31 - Monitor Receiver State Diagram 79 Figure 32 - Le7920 SLIC/QLSLAC Device Application Circuit. 104

Zarlink Semiconductor Inc.

Le58QL061/063

Data Sheet

List of Tables

Table 1 - QLSLAC Device Features 8 Table 2 - 0 dBm0 Voltage Definitions with Unity Gain in X, R, GX, GR, AX and AR 18 Table 3 - PCM/GCI Mode Selection 35 Table 4 - Channel Parameters 50 Table 5 - Channel Monitors 52 Table 6 - Global Chip Parameters 52 Table 7 - Global Chip Status Monitors 52 Table 8 - GCI Channel Assignment Codes 72 Table 9 - Generic Byte Transmission Sequence 80 Table 10 - Byte Transmission Sequence for TOP Command. 83 Table 11 - General Transmission Sequence of SOP Command 83 Table 12 - Generic Transmission Sequence for COP Command. 90 Table 13 - A-Law Positive Input Values. 101 Table 14 - µ-Law Positive Input Values 102

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Datasheet ID: LE58QL063HVC 648974