M2GL025-1FGG484T1

M2GL025-1FGG484T1 Datasheet

M2GL005 S M2GL010 S/T/TS M2GL025 T/TS M2GL050 T/TS M2GL060 T/TS M2GL090 T/TS M2GL150 T/TS

Part	Datasheet
M2GL025-1FGG484T1	M2GL025-1FGG484T1 (pdf)

Related Parts	Information
M2S010S-1TQG144I	M2S010S-1TQG144I
M2S010S-1TQ144I	M2S010S-1TQ144I
M2S010S-1TQ144	M2S010S-1TQ144
M2S010S-1TQG144	M2S010S-1TQG144
M2S010S-TQ144I	M2S010S-TQ144I
M2S010S-TQG144I	M2S010S-TQG144I
M2S010S-TQG144	M2S010S-TQG144
M2GL060-1FGG484T1	M2GL060-1FGG484T1
M2GL060TS-1FGG676T2	M2GL060TS-1FGG676T2
M2GL060TS-1FGG484T2	M2GL060TS-1FGG484T2
M2GL060TS-1VFG400T2	M2GL060TS-1VFG400T2
M2GL090TS-1FGG676T2	M2GL090TS-1FGG676T2
M2GL060TS-1FGG484M	M2GL060TS-1FGG484M
M2GL060TS-1FG484M	M2GL060TS-1FG484M
M2GL090TS-1FGG484T2	M2GL090TS-1FGG484T2
M2GL060T-1FG484M	M2GL060T-1FG484M
M2GL060T-1FGG484M	M2GL060T-1FGG484M
M2GL090-1FGG484T1	M2GL090-1FGG484T1
M2GL010TS-1FGG484T2	M2GL010TS-1FGG484T2
M2GL010TS-1VFG400T2	M2GL010TS-1VFG400T2
M2GL010TS-1VFG256T2	M2GL010TS-1VFG256T2
M2S060T-1FGG676	M2S060T-1FGG676
M2GL025TS-1FGG484T2	M2GL025TS-1FGG484T2
M2GL025TS-1VFG400T2	M2GL025TS-1VFG400T2
M2GL010-1FGG484T1	M2GL010-1FGG484T1
M2GL025TS-1VFG256T2	M2GL025TS-1VFG256T2
M2GL005-TQG144I	M2GL005-TQG144I
M2GL010S-1TQ144	M2GL010S-1TQ144
M2GL010S-TQG144	M2GL010S-TQG144
M2GL010S-1TQG144	M2GL010S-1TQG144
M2GL010S-TQ144I	M2GL010S-TQ144I
M2GL010S-TQG144I	M2GL010S-TQG144I
M2GL010S-1TQG144I	M2GL010S-1TQG144I
M2GL010S-TQ144	M2GL010S-TQ144
M2GL010S-1TQ144I	M2GL010S-1TQ144I

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IGLOO2 FPGAs Product Brief PB0121 Product Brief Microsemi FPGAs integrate fourth generation flash-based FPGA fabric and high-performance communications interfaces on a single chip. The IGLOO2 family is the industry’s lowest power, most reliable and highest security programmable logic solution. This next generation IGLOO2 architecture offers up to 3.6X gate count implemented with 4-input look-up table LUT fabric with carry chains, giving 2X performance, and includes multiple embedded memory options and mathblocks for digital signal processing DSP . High speed serial interfaces include PCI EXPRESS PCIe , 10 Gbps attachment unit interface XAUI / XGMII extended sublayer XGXS plus native serialization/deserialization SERDES communication, while double data rate 2 DDR2 /DDR3 memory controllers provide high speed memory interfaces. IGLOO2 Family High-Performance FPGA • Efficient 4-Input LUTs with Carry Chains for High-Performance and Low Power • Up to 236 Blocks of Dual-Port 18 Kbit SRAM Large SRAM with 400 MHz Synchronous Performance 512 x 36, 512 x 32, 1 Kbit x 18, 1 Kbit x 16, 2 Kbit x 9, 2 Kbit x 8, 4 Kbit x 4, 8 Kbit x 2, or 16 Kbit x 1 • Up to 240 Blocks of Three-Port 1 Kbit SRAM with 2 Read Ports and 1 Write Port micro SRAM • High-Performance DSP Up to 240 Fast mathblocks with 18 x 18 Signed Multiplication, 17 x 17 Unsigned Multiplication and 44-Bit Accumulator High Speed Serial Interfaces • Up to 16 SERDES Lanes, Each Supporting: XGXS/XAUI Extension To Implement a 10 Gbps XGMII Ethernet PHY Interface Native SERDES Interface Facilitates Implementation of Serial RapidIO in Fabric or an SGMII Interface to a soft Ethernet MAC PCI Express PCIe Endpoint Controller x1, x2, x4 Lane PCI Express Core Up to 2 Kbytes Maximum Payload Size 64-/32-Bit AXI/AHB Master and Slave Interfaces to the Application Layer High Speed Memory Interfaces • Up to 2 High Speed DDRx Memory Controllers HPMS DDR MDDR and Fabric DDR FDDR Controllers Supports LPDDR/DDR2/DDR3 Maximum 333 MHz Clock Rate SECDED Enable/Disable Feature Supports Various DRAM Bus Width Modes, x8, x9, x16, x18, x32, x36 Supports Command Reordering to Optimize Memory Efficiency Supports Data Reordering, Returning Critical Word First for Each Command • SDRAM Support through a Soft SDRAM Memory Controller High-Performance Memory Subsystem • 64 KB Embedded SRAM eSRAM • Up to 512 KB Embedded Nonvolatile Memory eNVM • One SPI/COMM_BLK • DDR Bridge 2 Port Data R/W Buffering Bridge to DDR Memory with 64-Bit AXI Interface • Non-Blocking, Multi-Layer AHB Bus Matrix Allowing Multi-Master Scheme Supporting 5 Masters and 7 Slaves June 2016 2016 Microsemi Corporation IGLOO2 FPGAs Product Brief • Two AHB/APB Interfaces to FPGA Fabric Master/Slave Capable • Two DMA Controllers to Offload Data Transactions 8-Channel Peripheral DMA PDMA for Data Transfer Between HPMS Peripherals and Memory • High-Performance DMA HPDMA for Data Transfer Between eSRAM and DDR Memories Clocking Resources • Clock Sources High Precision 32 kHz to 20 MHz Main Crystal Oscillator 1 MHz Embedded RC Oscillator 50 MHz Embedded RC Oscillator • Up to 8 Clock Conditioning Circuits CCCs with Up to 8 Integrated Analog PLLs Output Clock with 8 Output Phases and 45° Phase Difference Multiply/Divide, and Delay Capabilities • Frequency Input 1 MHz to 200 MHz, Output 20 MHz to 400 MHz Operating Voltage and I/Os • V Core Voltage • Multi-Standard User I/Os MSIO/MSIOD LVTTL/LVCMOS V MSIO only LVCMOS V, V, V, V DDR SSTL2_1, SSTL2_2 LVDS, MLVDS, Mini-LVDS, RSDS Differential Standards LVPECL receiver only • DDR I/Os DDRIO DDR, DDR2, DDR3, LPDDR, SSTL2, SSTL18, HSTL LVCMOS V, V, V, V • Market Leading Number of User I/Os with 5G SERDES Security • Design Security Features available on all devices Intellectual Property IP Protection through Unique Security Features and Use Models New to the PLD Industry Encrypted User Key and Bitstream Loading, Enabling Programming in Less-Trusted Locations Supply-Chain Assurance Device Certificate Enhanced Anti-Tamper Features Notes Mil Temp 010/025/050/060/090 devices are only available in the FG G 484 package. Mil Temp 150 devices are only available in the FC G 1152 package. 090 FCS G 325 is 11x13.5 pkg dimension. All the packages mentioned above are available with lead and lead free. G indicates that the package is RoHS 6/6 Compliant/Pb-free M2GL010 S device is only available in TQ G 144 package. M2GL010 T/TS devices are not available in TQ G 144 package. The M2GL090 T/TS device in the FCSG325 package is available with an ordering code of XZ48. The XZ48 ordering code pre-configures the device for Auto Update mode. Minimum Order quantities apply, contact your local Microsemi sales office for details. Shaded cells indicate that the device packages have vertical migration capability. Automotive T2 grade devices are available in the VF G 256, VF G 400, FG G 484, and FG G 676 packages. Automotive T1 grade devices are available in the FG G 484 package. The TQ G 144 package will be available in T2 grade by the end of February, Table 3 • Features per Device/Package Combination Package TQ G 144 8 VF G 256 8 FCS G 325 8 Devices M2GL005 S M2GL010 S M2GL005 S M2GL010 T/TS M2GL025 T/TS M2GL025 T/TS M2GL050 T/TS M2GL060 T/TS M2GL090 T/TS MDDR - x181 x182 x181 5G5 Crystal SERDES PCIe FDDR Oscillators Lanes Endpoints MSIO 3.3V max 6 52 50 119 66 94 90 114 104 MSIOD DDRIO 2.5V 2.5V Total User max 7 max IGLOO2 FPGAs Product Brief Table 3 • Features per Device/Package Combination continued VF G 400 8 M2GL005 S x181 M2GL010 T/TS x181 M2GL025 T/TS x181 M2GL050 T/TS x182 M2GL060 T/TS x181 FCV G 484 8 M2GL150 T/TS x181 FG G 484 8 M2GL005 S x181 M2GL010 T/TS x181 M2GL025 T/TS x181 M2GL050 T/TS x182 M2GL060 T/TS x181 M2GL090 T/TS x181 FC G 536 8 M2GL150 T/TS x181 FG G 676 8 M2GL060 T/TS x181 M2GL090 T/TS x181 FG G 896 8, 10 M2GL050 T/TS x364 FC G 1152 8 M2GL150 T/TS x363 292 106 176 IGLOO2 Ordering Information Flash_GOLDEN_N System Controller SPI Port M2GL050 TS Application Temperature Range Blank = Commercial 0°C to +85°C Junction Temperature I = Industrial to +100°C Junction Temperature M = Military to +125°C Junction Temperature T1 = AEC-Q100 Automotive Grade 1 to 135°C Junction Temperature T2 = AEC-Q100 Automotive Grade 2 to 125°C Junction Temperature Package Lead Count RoHS Status Blank = RoHs 5/6 Compliant / Package contains Pb Lead Package Type G = RoHS 6/6 Compliant / Pb-free packaging FG = Fine Pitch Ball Grid Array mm pitch VF = Very Fine Pitch Ball Grid Array mm pitch FC = Flip Chip Ball Grid Array mm pitch FCS = Flip Chip Ball Grid Array mm pitch FCV = Very Fine Pitch Flip Chip Ball Grid Array mm pitch TQ = Thin Quad Flat Pack Rectangular Package mm pitch Speed Grade Blank = PCIe Gen 1 Support Only Standard Speed Grade 1 = 15 % Faster than STD, PCIe Gen 1 and Gen 2 Prefix Blank = Design Security TS = Transceiver, Design, and Data Security T = Transceiver and Design Security S = Design and Data Security Part Number Digits indicate approximate number of LUTs in Thousands M2GL005 * M2GL010 M2GL025 M2GL050 M2GL060 M2GL090 M2GL150 Notes *M2GL005 devices are not available with Transceivers or in the Military temperature grade. Automotive grade devices are available with S/TS. VIII IGLOO2 FPGAs Product Brief IGLOO2 Commercial and Industrial Temperature Grade Devices Table 6 • IGLOO2 Devices without Data Security All Speed Grades, C and I Temperature 1 Density FCS G 325 VF G 256 FCS G 536 VF G 400 FCV G 484 TQ G 144 FG G 484 FG G 676 FG G 896 FC G 1152 M2GL005 M2GL010 M2GL025 M2GL050 M2GL060 M2GL090 M2GL150 Notes All the packages mentioned above are available with lead and lead free. G indicates that the package is RoHS 6/6 Compliant/Pb-free. T indicates that the devices are available with Transceiver. Example ordering code M2GL025T-FCSG325 Shaded cells indicate that the devices are available without Transceiver. Example ordering code M2GL025-FCSG325 Table 7 • IGLOO2 Data Security "S" Devices All Speed Grades, C and I Temperature 1 Density FCS G 325 VF G 256 FCS G 536 VF G 400 FCV G 484 TQ G 144 FG G 484 FG G 676 FG G 896 FC G 1152 M2GL005 M2GL010 M2GL025 M2GL050 M2GL060 M2GL090 M2GL150 Notes All the packages mentioned above are available with lead and lead free. G indicates that the package is RoHS 6/6 Compliant/Pb-free. S indicates that the devices are available with Data Security. Example ordering code M2GL005S-VFG400 TS indicates that the devices are available with Transceiver and Data Security. Example ordering code M2GL025TS-FCSG325 IGLOO2 FPGAs Product Brief IGLOO2 Military Temperature Grade Devices Table 8 • IGLOO2 Military Temperature Device Offering M2GL010 T/TS -1FG G 484M M2GL025 T/TS -1FG G 484M M2GL050 T/TS -1FG G 484M M2GL060 T/TS -1FG G 484M M2GL090 T/TS -1FG G 484M M2GL150 T/TS -1FC G 1152M Notes Gold Wire bonds are available for the FG484 package by appending X399 to the part number when ordering, for example: M2GL090 T/TS -1FG484MX399. All the packages mentioned above are available with lead and lead free. G indicates that the package is RoHS 6/6 Compliant/Pb-free. IGLOO2 Device Status Refer to the DS0128 IGLOO2 and SmartFusion2 Datasheet for device status. IGLOO2 Datasheet and Pin Descriptions The datasheet and pin descriptions are published separately • DS0128 IGLOO2 and SmartFusion2 Datasheet • DS0124 IGLOO2 Pin Descriptions Datasheet • DS0138 IGLOO2 Automotive Grade 1 Datasheet • DS0134 SmartFusion2 and IGLOO2 Automotive Grade 2 Datasheet • PB0135 Automotive Grade 2 IGLOO2 FPGAs Product Brief Marking Specification Details Microsemi normally topside marks the full ordering part number on each device. The figure below provides the details for each character code present on Microsemi’s IGLOO2 FPGA devices. Device Name Package Wafer Lot# Speed Grade Product Grade Date Code Customer Type Number Part Number Prefix Country of Origin IGLOO2 FPGAs Product Brief • Device Name M2XXXX M2GL for IGLOO2 Devices Example M2GL050TS • Package PK### Available Package as below PK Package code† FG G Fine Pitch BGA, mm pitch FC G Flip Chip Fine Pitch BGA with Metal LID on top, mm pitch FCV G Flip Chip Very Fine Pitch BGA with Metal LID on top, mm pitch FCS G Flip Chip Ultra Fine Pitch BGA with Metal LID on top, mm pitch VF G Very Fine Pitch BGA, mm pitch TQ G Ultra Fine Pitch Thin Quad Flat Pack Package, mm pitch ### Number of Pins Can be three or four digits. For example,144, 256, or 1152 • Speed Grade -## Speed Binning Number Blank Standard speed grade -1 -1 Speed grade • Product grade Z Product Grade assigned as follows Blank/C Commercial ES Engineering Samples I Industrial M Military Temperature PP Pre Production T1 AEC-Q100 Automotive Grade 1 T2 AEC-Q100 Automotive Grade 2 • Date Code YYWWSS% Assembly Date Code YY Last two digits for seal year WW Work week the part was sealed SS Two blank spaces % Can be digital number or character for new product • Customer Type Number As specified on lot traveler GW Gold Wire bond • Part number Prefix Part number prefix, assigned as below Blank Design Security T Transceivers and Design Security S Design and Data Security TS Transceiver, Design, and Data Security † All the packages mentioned above are available with lead and lead free. G indicates that the package is RoHS 6/6 Compliant/Pb-free. IGLOO2 FPGAs Product Brief • Country of Origin CCD Assembly house country location Country name Country Code China CHN Hong Kong HKG Japan JPN Korea, South KOR Philippines PHL Taiwan TWN Singapore SGP United States USA Malaysia MYS 1 IGLOO2 Device Family Overview Microsemi’s IGLOO2 FPGAs integrate fourth generation flash-based FPGA fabric and high-performance communications interfaces on a single chip. The IGLOO2 family is the industry’s lowest power, highest reliability and most secure programmable logic solution. This next generation IGLOO2 architecture offers up to 3.6X gate count, implemented with 4-input look-up table LUT fabric with carry chains, giving 2X performance, and includes multiple embedded memory options and mathblocks for DSP. High speed serial interfaces enable PCIe, XAUI / XGXS plus native SERDES communication while DDR2/DDR3 memory controllers provide high speed memory interfaces. Reliability IGLOO2 flash-based fabric has zero FIT configuration rate due to its single event upset SEU immunity, which is critical in reliability applications. The flash fabric also has the advantage that no external configuration memory is required, making the device instant-on it retains configuration when powered off. To complement this unique FPGA capability, IGLOO2 devices add reliability to many other aspects of the device. Single Error Correct Double Error Detect SECDED protection is implemented on the embedded SRAM eSRAM , and is optional on the DDR memory controllers. This means that if a one-bit error is detected, it will be corrected. Errors of more than one bit are detected only and not corrected. SECDED error signals are brought to the FPGA fabric to allow the user to monitor the status of these protected internal memories. Other areas of the architecture are implemented with latches, which are more resistant to SEUs. Therefore, no correction is needed in these locations DDR bridges HPMS, MDDR, FDDR , SPI, and PCIe FIFOs. Highest Security Devices Building further on the intrinsic security benefits of flash nonvolatile memory technology, the IGLOO2 family incorporates essentially all the legacy security features that made the original and third-generation flash FPGAs and cSoCs the gold standard for secure devices in the PLD industry. In addition, the fourth-generation flash-based SmartFusion2 and IGLOO2 FPGAs add many unique design and data security features and use models new to the PLD industry. Design Security vs. Data Security When classifying security attributes of programmable logic devices PLDs , a useful distinction is made between design security and data security. IGLOO2 FPGAs Product Brief Design Security Design security is protecting the intent of the owner of the design, such as keeping the design and associated bitstream keys confidential, preventing design changes for example, insertion of Trojan Horses , and controlling the number of copies made throughout the device life cycle. Design security may also be known as intellectual property IP protection. It is one aspect of antitamper AT protection. Design security applies to the device from initial production, includes any updates such as in-the-field upgrades, and can include decommissioning of the device at the end of its life, if desired. Good design security is a prerequisite for good data security. The following are the main design security features supported. Table 1-1 • Design Security Features All Devices M2GL005 M2GL060 M2GL010 M2GL090 M2GL025 M2GL150 M2GL050 FlashLock Passcode Security 256-bit Flexible security settings using flash lock-bits Encrypted/Authenticated Design Key Loading width mode • Supports memory densities up to 4 GB • Supports a maximum of 8 memory banks • SECDED enable/disable feature • Embedded physical interface PHY • Read and Write buffers in fully associative CAMs, configurable in powers of 2, up to 64 Reads plus 64 Writes • Support for dynamically changing clock frequency while in self-refresh • Supports command reordering to optimize memory efficiency • Supports data reordering, returning critical word first for each command MDDR Subsystem The MDDR subsystem has two interfaces to the DDR. One is an AXI 64-bit bus from the DDR bridge within the HPMS. The other is a multiplexed interface from the FPGA fabric, which can be configured as either a single AXI 64-bit bus or two 32-bit AHB-Lite buses. There is also a 16-bit APB configuration bus, which is used to initialize the majority of the internal registers within the MDDR subsystem after reset. This APB configuration bus is mastered by a master in the FPGA fabric. Support for V Single Data Rate DRAMs SDRAM can be obtained by instantiating a soft AHB or AXI SDRAM memory controller in the FPGA fabric and connecting I/O ports to V MSIO. FDDR Subsystem The FDDR subsystem has one interface to the DDR. This is a multiplexed interface from the FPGA fabric, which can be configured as either a single AXI 64-bit bus or two 32-bit AHB-Lite buses. There is also a 16-bit APB configuration bus, which is used to initialize the majority of the internal registers within the FDDR subsystem after reset. This APB configuration bus can be mastered by a master in the FPGA fabric. IGLOO2 Device Family Overview IGLOO2 Development Tools Design Software Microsemi's System-on-Chip SoC is a comprehensive software toolset to design applications using the IGLOO2 device. Libero SoC manages the entire design flow from design entry, synthesis and simulation, place and route, timing and power analysis, with enhanced integration of the embedded design flow. System designers can leverage the easy-to-use Libero SoC that includes the following features: • System Builder for creation of system level architecture • Synthesis, DSP and debug support from Synopsys • Simulation from Mentor Graphics • Push-button design flow with power analysis and timing analysis • SmartDebug for access to non-invasive probes within the IGLOO2 devices For more information, refer to Libero SoC. Design Hardware Microsemi’s IGLOO2 Evaluation kit M2GL-EVAL-KIT , is a low-cost platform to evaluate various features offered by the IGLOO2 devices Figure The kit includes a M2GL010T-1FGG484 device. The board includes an RJ45 interface to 10/100/1000 Ethernet, 512 Mb of LPDDR, 64 Mb SPI Flash, USB-UART connections as well as I2C, SPI and GPIO headers. The kit includes a 12 V power supply but can also be powered via the PCIe edge connector. The kit also includes a FlashPro4 JTAG programmer for programming and debugging. Figure 1-1 • IGLOO2 Evaluation Kit IP Cores Microsemi offers many soft peripherals that can be placed in the FPGA fabric of the device. These include Core429, Core1553, CoreJESD204BRX/TX, CoreFRI, CoreFFT, and many other DirectCores. Refer to IP Cores for more information. 2 Product Brief Information List of Changes Changes Updated Table 1 and Table 2 for grade 1 and 2 entries SAR 1-IV, 1-V Updated the "IGLOO2 Ordering Information" image for grade 1 and 2 entries 1-IX Added the grade 1 and grade 2 references in "IGLOO2 Datasheet and Pin Descriptions" SAR Added grade 1 and 2 entries in "Description" SAR 1-XI 1-XII Updated Table 3 with more footnotes. SAR 66079, SAR 77444, and SAR Updated Table 1 SAR Updated "Marking Specification Details" SAR Updated "Low Power" SAR Updated Table 2 SAR Added Table 5, Table 6, and Table 7 SAR Updated "Marking Specification Details" SAR V VIII, X, X XI Updated Table 1, Table 2, Table 3, Table 4, and Table 8 IV, V, V, VII, XI Removed all instances of and references to M2GL100. VQ144 is replaced with TQ144 SAR Updated Table 1-1 and Table 1-2 Updated "IGLOO2 Ordering Information" Added "IGLOO2 Development Tools" 1-2 and 1-3 IX 1-9 Updated Device Packages 005-VF256 and 150-FCS536 in Table Updated Table 2, Table 3, and Table V, VII Table 1 to Table 4 and "IGLOO2 Ordering Information" were update with IV, VIII Military device data. The "Marking Specification Details" section and the X, VII "Available Programming Interfaces" table were added. Tables 3-6 were combined into Table Fabric Interface Controller features VII, IV were added to "IGLOO2 FPGA Product Family" table. Packages VQ144 and V, VII FCV484 were added to Table 2 and Table The Data Security Features section, table and the Device Status table were N/A, III removed. “IGLOO2 FPGA Block Diagram” was updated. Packages FCS325 and VF256 were added to "I/Os Per Package". "IGLOO2 V, III Ordering Information" was updated. Typo fixed in "IGLOO2 FPGA Block Diagram". Product Brief Information Changes LSRAM x32/36 widths added. "IGLOO2 FPGA Product Family" table note IV, added referring to updates in Table 4 "IGLOO2 Ordering Information" was updated. Part Numbers tables 7 and 8 VIII, XI were removed. "IGLOO2 Device Status" section was updated. M2GL090-FG676 and M2GL005-VF400 package pinouts finalized. Initial release IGLOO2 FPGAs Product Brief Datasheet Categories Categories In order to provide the latest information to designers, some datasheet parameters are published before data has been fully characterized from silicon devices. The data provided for a given device, as highlighted in the "IGLOO2 Device Status", is designated as either "Product Brief," "Advance," "Preliminary," or "Production." The definitions of these categories are as follows: The product brief is a summarized version of a datasheet advance or production and contains general product information. This document gives an overview of specific device and family information. Advance This version contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, but not for production. This label only applies to the DC and Switching Characteristics chapter of the datasheet and will only be used when the data has not been fully characterized. The datasheet contains information based on simulation and/or initial characterization. The information is believed to be correct, but changes are possible. Production This version contains information that is considered to be final. Export Administration Regulations EAR The products described in this document are subject to the Export Administration Regulations EAR . They could require an approved export license prior to export from the United States. An export includes release of product or disclosure of technology to a foreign national inside or outside the United States. Safety Critical, Life Support, and High-Reliability Applications Policy The products described in this advance status document may not have completed the Microsemi qualification process. Products may be amended or enhanced during the product introduction and qualification process, resulting in changes in device functionality or performance. It is the responsibility of each customer to ensure the fitness of any product but especially a new product for a particular purpose, including appropriateness for safety-critical, life-support, and other high-reliability applications. Consult the Microsemi SoC Products Group Terms and Conditions for specific liability exclusions relating to life-support applications. Refer to the Reliability Report for all of the SoC Products Group’s products. Microsemi also offers a variety of enhanced qualification and lot acceptance screening procedures. Contact your local sales office for additional reliability information. Microsemi Corporate Headquarters One Enterprise, Aliso Viejo, CA 92656 USA. Within the USA +1 949 380-6100 Sales +1 949 380-6136 Fax +1 949 215-4996 Microsemi Corporate Headquarters One Enterprise, Aliso Viejo, CA 92656 USA Within the USA +1 800 713-4113 Outside the USA +1 949 380-6100 Sales +1 949 380-6136 Fax +1 949 215-4996 E-mail: 2016 Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are trademarks of Microsemi Corporation. All other trademarks and service marks are the property of their respective owners. Microsemi makes no warranty, representation, or guarantee regarding the information contained herein or the suitability of its products and services for any particular purpose, nor does Microsemi assume any liability whatsoever arising out of the application or use of any product or circuit. The products sold hereunder and any other products sold by Microsemi have been subject to limited testing and should not be used in conjunction with mission-critical equipment or applications. Any performance specifications are believed to be reliable but are not verified, and Buyer must conduct and complete all performance and other testing of the products, alone and together with, or installed in, any end-products. Buyer shall not rely on any data and performance specifications or parameters provided by Microsemi. It is the Buyer's responsibility to independently determine suitability of any products and to test and verify the same. The information provided by Microsemi hereunder is provided “as is, where is” and with all faults, and the entire risk associated with such information is entirely with the Buyer. Microsemi does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other IP rights, whether with regard to such information itself or anything described by such information. Information provided in this document is proprietary to Microsemi, and Microsemi reserves the right to make any changes to the information in this document or to any products and services at any time without notice. About Microsemi Microsemi Corporation Nasdaq MSCC offers a comprehensive portfolio of semiconductor and system solutions for aerospace & defense, communications, data center and industrial markets. Products include high-performance and radiation-hardened analog mixed-signal integrated circuits, FPGAs, SoCs and ASICs power management products timing and synchronization devices and precise time solutions, setting the world's standard for time voice processing devices RF solutions discrete components enterprise storage and communication solutions, security technologies and scalable anti-tamper products Ethernet solutions Power-over-Ethernet ICs and midspans as well as custom design capabilities and services. Microsemi is headquartered in Aliso Viejo, Calif., and has approximately 4,800 employees globally. Learn more at

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IGLOO2 FPGAs Product Brief

PB0121 Product Brief

Microsemi FPGAs integrate fourth generation flash-based FPGA fabric and high-performance communications interfaces on a single chip. The IGLOO2 family is the industry’s lowest power, most reliable and highest security programmable logic solution. This next generation IGLOO2 architecture offers up to 3.6X gate count implemented with 4-input look-up table LUT fabric with carry chains, giving 2X performance, and includes multiple embedded memory options and mathblocks for digital signal processing DSP . High speed serial interfaces include PCI EXPRESS PCIe , 10 Gbps attachment unit interface XAUI / XGMII extended sublayer XGXS plus native serialization/deserialization SERDES communication, while double data rate 2 DDR2 /DDR3 memory controllers provide high speed memory interfaces.

IGLOO2 Family

High-Performance FPGA
• Efficient 4-Input LUTs with Carry Chains for High-Performance and Low Power
• Up to 236 Blocks of Dual-Port 18 Kbit SRAM Large SRAM with 400 MHz Synchronous Performance 512 x 36, 512 x 32, 1 Kbit x 18, 1 Kbit x 16, 2 Kbit x 9, 2 Kbit x 8, 4 Kbit x 4, 8 Kbit x 2, or 16 Kbit x 1
• Up to 240 Blocks of Three-Port 1 Kbit SRAM with 2 Read Ports and 1 Write Port micro SRAM
• High-Performance DSP

Up to 240 Fast mathblocks with 18 x 18 Signed Multiplication, 17 x 17 Unsigned Multiplication and 44-Bit Accumulator

High Speed Serial Interfaces
• Up to 16 SERDES Lanes, Each Supporting:

XGXS/XAUI Extension To Implement a 10 Gbps XGMII Ethernet PHY Interface

Native SERDES Interface Facilitates Implementation of Serial RapidIO in Fabric or an SGMII Interface to a soft Ethernet MAC

PCI Express PCIe Endpoint Controller
x1, x2, x4 Lane PCI Express Core

Up to 2 Kbytes Maximum Payload Size
64-/32-Bit AXI/AHB Master and Slave Interfaces to the Application Layer

High Speed Memory Interfaces
• Up to 2 High Speed DDRx Memory Controllers

HPMS DDR MDDR and Fabric DDR FDDR Controllers

Supports LPDDR/DDR2/DDR3

Maximum 333 MHz Clock Rate

SECDED Enable/Disable Feature

Supports Various DRAM Bus Width Modes, x8, x9, x16, x18, x32, x36
Supports Command Reordering to Optimize Memory Efficiency
Supports Data Reordering, Returning Critical Word First for Each Command
• SDRAM Support through a Soft SDRAM Memory Controller

High-Performance Memory Subsystem
• 64 KB Embedded SRAM eSRAM
• Up to 512 KB Embedded Nonvolatile Memory eNVM
• One SPI/COMM_BLK
• DDR Bridge 2 Port Data R/W Buffering Bridge to DDR Memory with 64-Bit AXI Interface
• Non-Blocking, Multi-Layer AHB Bus Matrix Allowing Multi-Master Scheme Supporting 5 Masters and 7 Slaves

June 2016
2016 Microsemi Corporation

IGLOO2 FPGAs Product Brief
• Two AHB/APB Interfaces to FPGA Fabric Master/Slave Capable
• Two DMA Controllers to Offload Data Transactions
8-Channel Peripheral DMA PDMA for Data Transfer Between HPMS Peripherals and Memory
• High-Performance DMA HPDMA for Data Transfer Between eSRAM and DDR Memories

Clocking Resources
• Clock Sources

High Precision 32 kHz to 20 MHz Main Crystal Oscillator
1 MHz Embedded RC Oscillator
50 MHz Embedded RC Oscillator
• Up to 8 Clock Conditioning Circuits CCCs with Up to 8 Integrated Analog PLLs

Output Clock with 8 Output Phases and 45° Phase Difference Multiply/Divide, and Delay Capabilities
• Frequency Input 1 MHz to 200 MHz, Output 20 MHz to 400 MHz

Operating Voltage and I/Os
• V Core Voltage
• Multi-Standard User I/Os MSIO/MSIOD

LVTTL/LVCMOS V MSIO only

LVCMOS V, V, V, V

DDR SSTL2_1, SSTL2_2

LVDS, MLVDS, Mini-LVDS, RSDS Differential Standards

LVPECL receiver only
• DDR I/Os DDRIO

DDR, DDR2, DDR3, LPDDR, SSTL2, SSTL18, HSTL

LVCMOS V, V, V, V
• Market Leading Number of User I/Os with 5G SERDES

Security
• Design Security Features available on all devices

Intellectual Property IP Protection through Unique Security Features and Use Models New to the PLD Industry

Encrypted User Key and Bitstream Loading, Enabling Programming in Less-Trusted Locations

Supply-Chain Assurance Device Certificate

Enhanced Anti-Tamper Features
Notes Mil Temp 010/025/050/060/090 devices are only available in the FG G 484 package. Mil Temp 150 devices are only available in the FC G 1152 package. 090 FCS G 325 is 11x13.5 pkg dimension. All the packages mentioned above are available with lead and lead free. G indicates that the package is RoHS 6/6 Compliant/Pb-free M2GL010 S device is only available in TQ G 144 package. M2GL010 T/TS devices are not available in TQ G 144 package. The M2GL090 T/TS device in the FCSG325 package is available with an ordering code of XZ48. The XZ48 ordering code
pre-configures the device for Auto Update mode. Minimum Order quantities apply, contact your local Microsemi sales office for details. Shaded cells indicate that the device packages have vertical migration capability. Automotive T2 grade devices are available in the VF G 256, VF G 400, FG G 484, and FG G 676 packages. Automotive T1 grade devices are available in the FG G 484 package. The TQ G 144 package will be available in T2 grade by the end of February,

Table 3
• Features per Device/Package Combination

Package TQ G 144 8 VF G 256 8

FCS G 325 8

Devices M2GL005 S M2GL010 S M2GL005 S M2GL010 T/TS M2GL025 T/TS M2GL025 T/TS M2GL050 T/TS M2GL060 T/TS M2GL090 T/TS

MDDR -
x181 x182 x181
5G5 Crystal SERDES PCIe FDDR Oscillators Lanes Endpoints

MSIO 3.3V max 6
52 50 119 66 94 90 114 104

MSIOD DDRIO
2.5V 2.5V Total User
max 7 max

IGLOO2 FPGAs Product Brief

Table 3
• Features per Device/Package Combination continued

VF G 400 8

M2GL005 S
x181

M2GL010 T/TS x181

M2GL025 T/TS x181

M2GL050 T/TS x182

M2GL060 T/TS x181

FCV G 484 8 M2GL150 T/TS x181

FG G 484 8

M2GL005 S
x181

M2GL010 T/TS x181

M2GL025 T/TS x181

M2GL050 T/TS x182

M2GL060 T/TS x181

M2GL090 T/TS x181

FC G 536 8

M2GL150 T/TS x181

FG G 676 8

M2GL060 T/TS x181

M2GL090 T/TS x181

FG G 896 8, 10 M2GL050 T/TS
x364

FC G 1152 8 M2GL150 T/TS x363
292 106 176
IGLOO2 Ordering Information

Flash_GOLDEN_N System Controller SPI Port

M2GL050 TS

Application Temperature Range

Blank = Commercial 0°C to +85°C Junction Temperature I = Industrial to +100°C Junction Temperature M = Military to +125°C Junction Temperature

T1 = AEC-Q100 Automotive Grade 1 to 135°C Junction Temperature T2 = AEC-Q100 Automotive Grade 2 to 125°C Junction Temperature

Package Lead Count

RoHS Status

Blank = RoHs 5/6 Compliant / Package contains Pb Lead

Package Type

G = RoHS 6/6 Compliant / Pb-free packaging

FG = Fine Pitch Ball Grid Array mm pitch VF = Very Fine Pitch Ball Grid Array mm pitch FC = Flip Chip Ball Grid Array mm pitch FCS = Flip Chip Ball Grid Array mm pitch FCV = Very Fine Pitch Flip Chip Ball Grid Array mm pitch TQ = Thin Quad Flat Pack Rectangular Package mm pitch

Speed Grade

Blank = PCIe Gen 1 Support Only Standard Speed Grade 1 = 15 % Faster than STD, PCIe Gen 1 and Gen 2

Prefix

Blank = Design Security TS = Transceiver, Design, and Data Security T = Transceiver and Design Security S = Design and Data Security

Part Number Digits indicate approximate number of LUTs in Thousands M2GL005 * M2GL010

M2GL025

M2GL050

M2GL060 M2GL090 M2GL150

Notes *M2GL005 devices are not available with Transceivers or in the Military temperature grade. Automotive grade devices are available with S/TS.

VIII

IGLOO2 FPGAs Product Brief

IGLOO2 Commercial and Industrial Temperature Grade Devices

Table 6
• IGLOO2 Devices without Data Security All Speed Grades, C and I Temperature 1

Density FCS G 325 VF G 256 FCS G 536 VF G 400 FCV G 484 TQ G 144 FG G 484 FG G 676 FG G 896 FC G 1152

M2GL005

M2GL010

M2GL025

M2GL050

M2GL060

M2GL090

M2GL150

Notes All the packages mentioned above are available with lead and lead free. G indicates that the package is
RoHS 6/6 Compliant/Pb-free. T indicates that the devices are available with Transceiver. Example ordering code M2GL025T-FCSG325 Shaded cells indicate that the devices are available without Transceiver. Example ordering code M2GL025-FCSG325

Table 7
• IGLOO2 Data Security "S" Devices All Speed Grades, C and I Temperature 1

Density FCS G 325 VF G 256 FCS G 536 VF G 400 FCV G 484 TQ G 144 FG G 484 FG G 676 FG G 896 FC G 1152

M2GL005

M2GL010

M2GL025

M2GL050

M2GL060

M2GL090

M2GL150

Notes All the packages mentioned above are available with lead and lead free. G indicates that the package is
RoHS 6/6 Compliant/Pb-free. S indicates that the devices are available with Data Security. Example ordering code M2GL005S-VFG400 TS indicates that the devices are available with Transceiver and Data Security. Example ordering code M2GL025TS-FCSG325

IGLOO2 FPGAs Product Brief

IGLOO2 Military Temperature Grade Devices

Table 8
• IGLOO2 Military Temperature Device Offering M2GL010 T/TS -1FG G 484M M2GL025 T/TS -1FG G 484M M2GL050 T/TS -1FG G 484M M2GL060 T/TS -1FG G 484M M2GL090 T/TS -1FG G 484M M2GL150 T/TS -1FC G 1152M
Notes Gold Wire bonds are available for the FG484 package by appending X399 to the part number when ordering, for example:

M2GL090 T/TS -1FG484MX399. All the packages mentioned above are available with lead and lead free. G indicates that the package is RoHS 6/6

Compliant/Pb-free.

IGLOO2 Device Status

Refer to the DS0128 IGLOO2 and SmartFusion2 Datasheet for device status.

IGLOO2 Datasheet and Pin Descriptions

The datasheet and pin descriptions are published separately
• DS0128 IGLOO2 and SmartFusion2 Datasheet
• DS0124 IGLOO2 Pin Descriptions Datasheet
• DS0138 IGLOO2 Automotive Grade 1 Datasheet
• DS0134 SmartFusion2 and IGLOO2 Automotive Grade 2 Datasheet
• PB0135 Automotive Grade 2 IGLOO2 FPGAs Product Brief

Marking Specification Details
Microsemi normally topside marks the full ordering part number on each device. The figure below provides the details for each character code present on Microsemi’s IGLOO2 FPGA devices.

Device Name Package

Wafer Lot# Speed Grade Product Grade

Date Code

Customer Type Number

Part Number Prefix Country of Origin

IGLOO2 FPGAs Product Brief
• Device Name M2XXXX M2GL for IGLOO2 Devices Example M2GL050TS
• Package PK### Available Package as below PK Package code† FG G Fine Pitch BGA, mm pitch FC G Flip Chip Fine Pitch BGA with Metal LID on top, mm pitch FCV G Flip Chip Very Fine Pitch BGA with Metal LID on top, mm pitch FCS G Flip Chip Ultra Fine Pitch BGA with Metal LID on top, mm pitch VF G Very Fine Pitch BGA, mm pitch TQ G Ultra Fine Pitch Thin Quad Flat Pack Package, mm pitch ### Number of Pins Can be three or four digits. For example,144, 256, or 1152
• Speed Grade -## Speed Binning Number Blank Standard speed grade -1 -1 Speed grade
• Product grade Z Product Grade assigned as follows Blank/C Commercial ES Engineering Samples I Industrial M Military Temperature PP Pre Production T1 AEC-Q100 Automotive Grade 1 T2 AEC-Q100 Automotive Grade 2
• Date Code YYWWSS% Assembly Date Code YY Last two digits for seal year WW Work week the part was sealed SS Two blank spaces % Can be digital number or character for new product
• Customer Type Number As specified on lot traveler GW Gold Wire bond
• Part number Prefix Part number prefix, assigned as below Blank Design Security T Transceivers and Design Security S Design and Data Security TS Transceiver, Design, and Data Security
† All the packages mentioned above are available with lead and lead free. G indicates that the package is RoHS 6/6 Compliant/Pb-free.

IGLOO2 FPGAs Product Brief
• Country of Origin CCD Assembly house country location Country name Country Code China CHN Hong Kong HKG Japan JPN Korea, South KOR Philippines PHL Taiwan TWN Singapore SGP United States USA Malaysia MYS
1 IGLOO2 Device Family Overview

Microsemi’s IGLOO2 FPGAs integrate fourth generation flash-based FPGA fabric and high-performance communications interfaces on a single chip. The IGLOO2 family is the industry’s lowest power, highest reliability and most secure programmable logic solution. This next generation IGLOO2 architecture offers up to 3.6X gate count, implemented with 4-input look-up table LUT fabric with carry chains, giving 2X performance, and includes multiple embedded memory options and mathblocks for DSP. High speed serial interfaces enable PCIe, XAUI / XGXS plus native SERDES communication while DDR2/DDR3 memory controllers provide high speed memory interfaces.

Reliability

IGLOO2 flash-based fabric has zero FIT configuration rate due to its single event upset SEU immunity, which is critical in reliability applications. The flash fabric also has the advantage that no external configuration memory is required, making the device instant-on it retains configuration when powered off. To complement this unique FPGA capability, IGLOO2 devices add reliability to many other aspects of the device. Single Error Correct Double Error Detect SECDED protection is implemented on the embedded SRAM eSRAM , and is optional on the DDR memory controllers. This means that if a one-bit error is detected, it will be corrected. Errors of more than one bit are detected only and not corrected. SECDED error signals are brought to the FPGA fabric to allow the user to monitor the status of these protected internal memories. Other areas of the architecture are implemented with latches, which are more resistant to SEUs. Therefore, no correction is needed in these locations DDR bridges HPMS, MDDR, FDDR , SPI, and PCIe FIFOs.

Highest Security Devices

Building further on the intrinsic security benefits of flash nonvolatile memory technology, the IGLOO2 family incorporates essentially all the legacy security features that made the original and third-generation flash FPGAs and cSoCs the gold standard for secure devices in the PLD industry. In addition, the fourth-generation flash-based SmartFusion2 and IGLOO2 FPGAs add many unique design and data security features and use models new to the PLD industry.

Design Security vs. Data Security

When classifying security attributes of programmable logic devices PLDs , a useful distinction is made between design security and data security.

IGLOO2 FPGAs Product Brief

Design Security

Design security is protecting the intent of the owner of the design, such as keeping the design and associated bitstream keys confidential, preventing design changes for example, insertion of Trojan Horses , and controlling the number of copies made throughout the device life cycle. Design security may also be known as intellectual property IP protection. It is one aspect of antitamper AT protection. Design security applies to the device from initial production, includes any updates such as in-the-field upgrades, and can include decommissioning of the device at the end of its life, if desired. Good design security is a prerequisite for good data security.

The following are the main design security features supported.

Table 1-1
• Design Security Features

All Devices

M2GL005

M2GL060

M2GL010

M2GL090

M2GL025

M2GL150

M2GL050

FlashLock Passcode Security 256-bit

Flexible security settings using flash lock-bits

Encrypted/Authenticated Design Key Loading
width mode
• Supports memory densities up to 4 GB
• Supports a maximum of 8 memory banks
• SECDED enable/disable feature
• Embedded physical interface PHY
• Read and Write buffers in fully associative CAMs, configurable in powers of 2, up to 64 Reads plus 64 Writes
• Support for dynamically changing clock frequency while in self-refresh
• Supports command reordering to optimize memory efficiency
• Supports data reordering, returning critical word first for each command

MDDR Subsystem

The MDDR subsystem has two interfaces to the DDR. One is an AXI 64-bit bus from the DDR bridge within the HPMS. The other is a multiplexed interface from the FPGA fabric, which can be configured as either a single AXI 64-bit bus or two 32-bit AHB-Lite buses. There is also a 16-bit APB configuration bus, which is used to initialize the majority of the internal registers within the MDDR subsystem after reset. This APB configuration bus is mastered by a master in the FPGA fabric. Support for V Single Data Rate DRAMs SDRAM can be obtained by instantiating a soft AHB or AXI SDRAM memory controller in the FPGA fabric and connecting I/O ports to V MSIO.

FDDR Subsystem

The FDDR subsystem has one interface to the DDR. This is a multiplexed interface from the FPGA fabric, which can be configured as either a single AXI 64-bit bus or two 32-bit AHB-Lite buses. There is also a 16-bit APB configuration bus, which is used to initialize the majority of the internal registers within the FDDR subsystem after reset. This APB configuration bus can be mastered by a master in the FPGA fabric.

IGLOO2 Device Family Overview

IGLOO2 Development Tools

Design Software

Microsemi's System-on-Chip SoC is a comprehensive software toolset to design applications using the IGLOO2 device. Libero SoC manages the entire design flow from design entry, synthesis and simulation, place and route, timing and power analysis, with enhanced integration of the embedded design flow. System designers can leverage the easy-to-use Libero SoC that includes the following features:
• System Builder for creation of system level architecture
• Synthesis, DSP and debug support from Synopsys
• Simulation from Mentor Graphics
• Push-button design flow with power analysis and timing analysis
• SmartDebug for access to non-invasive probes within the IGLOO2 devices For more information, refer to Libero SoC.

Design Hardware

Microsemi’s IGLOO2 Evaluation kit M2GL-EVAL-KIT , is a low-cost platform to evaluate various features offered by the IGLOO2 devices Figure The kit includes a M2GL010T-1FGG484 device. The board includes an RJ45 interface to 10/100/1000 Ethernet, 512 Mb of LPDDR, 64 Mb SPI Flash, USB-UART connections as well as I2C, SPI and GPIO headers. The kit includes a 12 V power supply but can also be powered via the PCIe edge connector. The kit also includes a FlashPro4 JTAG programmer for programming and debugging.

Figure 1-1
• IGLOO2 Evaluation Kit

IP Cores

Microsemi offers many soft peripherals that can be placed in the FPGA fabric of the device. These include Core429, Core1553, CoreJESD204BRX/TX, CoreFRI, CoreFFT, and many other DirectCores. Refer to IP Cores for more information.
2 Product Brief Information

List of Changes

Changes

Updated Table 1 and Table 2 for grade 1 and 2 entries SAR
1-IV, 1-V
Updated the "IGLOO2 Ordering Information" image for grade 1 and 2 entries
1-IX

Added the grade 1 and grade 2 references in "IGLOO2 Datasheet and Pin

Descriptions" SAR Added grade 1 and 2 entries in "Description" SAR
1-XI 1-XII

Updated Table 3 with more footnotes. SAR 66079, SAR 77444, and SAR

Updated Table 1 SAR

Updated "Marking Specification Details" SAR

Updated "Low Power" SAR

Updated Table 2 SAR Added Table 5, Table 6, and Table 7 SAR Updated "Marking Specification Details" SAR

V VIII, X, X XI

Updated Table 1, Table 2, Table 3, Table 4, and Table 8

IV, V, V, VII, XI

Removed all instances of and references to M2GL100. VQ144 is replaced
with TQ144 SAR Updated Table 1-1 and Table 1-2 Updated "IGLOO2 Ordering Information" Added "IGLOO2 Development Tools"
1-2 and 1-3 IX 1-9

Updated Device Packages 005-VF256 and 150-FCS536 in Table

Updated Table 2, Table 3, and Table

V, VII
Table 1 to Table 4 and "IGLOO2 Ordering Information" were update with IV, VIII Military device data. The "Marking Specification Details" section and the X, VII "Available Programming Interfaces" table were added.

Tables 3-6 were combined into Table Fabric Interface Controller features VII, IV were added to "IGLOO2 FPGA Product Family" table. Packages VQ144 and V, VII FCV484 were added to Table 2 and Table

The Data Security Features section, table and the Device Status table were N/A, III removed.
“IGLOO2 FPGA Block Diagram” was updated.
Packages FCS325 and VF256 were added to "I/Os Per Package". "IGLOO2 V, III Ordering Information" was updated. Typo fixed in "IGLOO2 FPGA Block Diagram".

Product Brief Information

Changes

LSRAM x32/36 widths added. "IGLOO2 FPGA Product Family" table note IV, added referring to updates in Table 4
"IGLOO2 Ordering Information" was updated. Part Numbers tables 7 and 8 VIII, XI were removed. "IGLOO2 Device Status" section was updated.

M2GL090-FG676 and M2GL005-VF400 package pinouts finalized.

Initial release

IGLOO2 FPGAs Product Brief

Datasheet Categories

Categories

In order to provide the latest information to designers, some datasheet parameters are published before data has been fully characterized from silicon devices. The data provided for a given device, as highlighted in the "IGLOO2 Device Status", is designated as either "Product Brief," "Advance," "Preliminary," or "Production." The definitions of these categories are as follows:

The product brief is a summarized version of a datasheet advance or production and contains general product information. This document gives an overview of specific device and family information.

Advance

This version contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, but not for production. This label only applies to the DC and Switching Characteristics chapter of the datasheet and will only be used when the data has not been fully characterized.

The datasheet contains information based on simulation and/or initial characterization. The information is believed to be correct, but changes are possible.

Production

This version contains information that is considered to be final.

Export Administration Regulations EAR

The products described in this document are subject to the Export Administration Regulations EAR . They could require an approved export license prior to export from the United States. An export includes release of product or disclosure of technology to a foreign national inside or outside the United States.

Safety Critical, Life Support, and High-Reliability Applications Policy

The products described in this advance status document may not have completed the Microsemi qualification process. Products may be amended or enhanced during the product introduction and qualification process, resulting in changes in device functionality or performance. It is the responsibility of each customer to ensure the fitness of any product but especially a new product for a particular purpose, including appropriateness for safety-critical, life-support, and other high-reliability applications. Consult the Microsemi SoC Products Group Terms and Conditions for specific liability exclusions relating to life-support applications. Refer to the Reliability Report for all of the SoC Products Group’s products. Microsemi also offers a variety of enhanced qualification and lot acceptance screening procedures. Contact your local sales office for additional reliability information.

Microsemi Corporate Headquarters

One Enterprise, Aliso Viejo, CA 92656 USA. Within the USA +1 949 380-6100 Sales +1 949 380-6136 Fax +1 949 215-4996

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Microsemi makes no warranty, representation, or guarantee regarding the information contained herein or the suitability of its products and services for any particular purpose, nor does Microsemi assume any liability whatsoever arising out of the application or use of any product or circuit. The products sold hereunder and any other products sold by Microsemi have been subject to limited testing and should not be used in conjunction with mission-critical equipment or applications. Any performance specifications are believed to be reliable but are not verified, and Buyer must conduct and complete all performance and other testing of the products, alone and together with, or installed in, any end-products. Buyer shall not rely on any data and performance specifications or parameters provided by Microsemi. It is the Buyer's responsibility to independently determine suitability of any products and to test and verify the same. The information provided by Microsemi hereunder is provided “as is, where is” and with all faults, and the entire risk associated with such information is entirely with the Buyer. Microsemi does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other IP rights, whether with regard to such information itself or anything described by such information. Information provided in this document is proprietary to Microsemi, and Microsemi reserves the right to make any changes to the information in this document or to any products and services at any time without notice.

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Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived M2GL025-1FGG484T1 Datasheet file may be downloaded here without warranties.

Datasheet ID: M2GL025-1FGG484T1 648969