A1010B-1PLG68I

A1010B-1PLG68I Datasheet

A1010B A1020B A10V10B A10V20B

Part	Datasheet
A1010B-1PLG68I	A1010B-1PLG68I (pdf)

Related Parts	Information
A1020B-2PLG44C	A1020B-2PLG44C
A1020B-2PLG68I	A1020B-2PLG68I
A1020B-PL84I	A1020B-PL84I
A10V20B-PLG68C	A10V20B-PLG68C
A1020B-1PL68C	A1020B-1PL68C
A1010B-2PL68C	A1010B-2PL68C
A1010B-1PL68I	A1010B-1PL68I
A1020B-PL68I	A1020B-PL68I
A1020B-1PL68I	A1020B-1PL68I
A1020B-2PL68I	A1020B-2PL68I
A1020B-PLG84C	A1020B-PLG84C
A1020B-1PLG44C	A1020B-1PLG44C
A1020B-1PLG68I	A1020B-1PLG68I
A1020B-2PL44C	A1020B-2PL44C
A1010B-2PLG44C	A1010B-2PLG44C
A1020B-PL84M	A1020B-PL84M
A1020B-PLG44C	A1020B-PLG44C
A1020B-PLG68C	A1020B-PLG68C
A1020B-1PLG84C	A1020B-1PLG84C
A1020B-2PLG44I	A1020B-2PLG44I
A1010B-2PLG44I	A1010B-2PLG44I
A1020B-PL44I	A1020B-PL44I
A1010B-1PL68C	A1010B-1PL68C
A1010B-PL44I	A1010B-PL44I
A1010B-PL68C	A1010B-PL68C
A1020B-PL68C	A1020B-PL68C
A1010B-1PLG44I	A1010B-1PLG44I
A1010B-2PLG68I	A1010B-2PLG68I
A1010B-PLG44C	A1010B-PLG44C
A1010B-PLG44I	A1010B-PLG44I
A1020B-2PLG84I	A1020B-2PLG84I
A1020B-1PL44C	A1020B-1PL44C
A1010B-2PL44I	A1010B-2PL44I
A1020B-2PL84C	A1020B-2PL84C
A1020B-1PL44I	A1020B-1PL44I
A10V20B-PL84C	A10V20B-PL84C
A1020B-PLG44I	A1020B-PLG44I
A1020B-1PLG44I	A1020B-1PLG44I
A1020B-2PL68C	A1020B-2PL68C
A1020B-1PLG84I	A1020B-1PLG84I
A1010B-1PL44I	A1010B-1PL44I
A1010B-2PL68I	A1010B-2PL68I
A1020B-1PL84M	A1020B-1PL84M
A1020B-PLG68I	A1020B-PLG68I
A1020B-2PL44I	A1020B-2PL44I
A1010B-1PL44C	A1010B-1PL44C
A1020B-2PLG84C	A1020B-2PLG84C
A1010B-1PLG44C	A1010B-1PLG44C
A1020B-PLG84M	A1020B-PLG84M
A10V20B-PL68C	A10V20B-PL68C
A1010B-PL44C	A1010B-PL44C
A1020B-PL84C	A1020B-PL84C
A1010B-1PLG68C	A1010B-1PLG68C
A1010B-PL68I	A1010B-PL68I
A1020B-1PLG68C	A1020B-1PLG68C
A1010B-PLG68I	A1010B-PLG68I
A1020B-PLG84I	A1020B-PLG84I
A1020B-1PLG84M	A1020B-1PLG84M
A10V20B-PLG84C	A10V20B-PLG84C
A1020B-1PL84I	A1020B-1PL84I
A1020B-2PL84I	A1020B-2PL84I
A1020B-1PL84C	A1020B-1PL84C
A1020B-2PLG68C	A1020B-2PLG68C
A1010B-2PL44C	A1010B-2PL44C
A1020B-PL44C	A1020B-PL44C
A10V10B-PLG68C	A10V10B-PLG68C
A1010B-2PLG68C	A1010B-2PLG68C
A1010B-PLG68C	A1010B-PLG68C
A10V10B-PL68C	A10V10B-PL68C
A1020B-PQ100C	A1020B-PQ100C
A1020B-VQG80I	A1020B-VQG80I
A1020B-2VQG80C	A1020B-2VQG80C
A1020B-2VQG80I	A1020B-2VQG80I
A1010B-2PQG100C	A1010B-2PQG100C
A1020B-1PQG100I	A1020B-1PQG100I
A1010B-PQ100I	A1010B-PQ100I
A1020B-PQG100I	A1020B-PQG100I
A1010B-1PQG100C	A1010B-1PQG100C
A1010B-VQ80C	A1010B-VQ80C
A1010B-2PQ100I	A1010B-2PQ100I
A1010B-PQ100C	A1010B-PQ100C
A1010B-PQG100I	A1010B-PQG100I
A1020B-PQG100C	A1020B-PQG100C
A1020B-2PQ100C	A1020B-2PQ100C
A1020B-2PQG100I	A1020B-2PQG100I
A1020B-1PQG100C	A1020B-1PQG100C
A1010B-2PQG100I	A1010B-2PQG100I
A1020B-1PQ100C	A1020B-1PQ100C
A1010B-2VQG80I	A1010B-2VQG80I
A1020B-2VQ80I	A1020B-2VQ80I
A1020B-2VQ80C	A1020B-2VQ80C
A1010B-2PQ100C	A1010B-2PQ100C
A1020B-1PQ100I	A1020B-1PQ100I
A1020B-2PQG100C	A1020B-2PQG100C
A1010B-2VQ80I	A1010B-2VQ80I
A1010B-PQG100C	A1010B-PQG100C
A1010B-VQG80I	A1010B-VQG80I
A1010B-1PQG100I	A1010B-1PQG100I
A1010B-1PQ100I	A1010B-1PQ100I
A1020B-VQ80I	A1020B-VQ80I
A1020B-PQ100I	A1020B-PQ100I
A1020B-2PQ100I	A1020B-2PQ100I
A1020B-1VQ80I	A1020B-1VQ80I
A1010B-1VQG80C	A1010B-1VQG80C
A1010B-1PQ100C	A1010B-1PQ100C
A1020B-VQ80C	A1020B-VQ80C
A1010B-VQG80C	A1010B-VQG80C
A1020B-1VQ80C	A1020B-1VQ80C
A10V20B-VQG80C	A10V20B-VQG80C
A1010B-1VQ80I	A1010B-1VQ80I
A10V10B-VQ80C	A10V10B-VQ80C
A10V20B-VQ80C	A10V20B-VQ80C
A1010B-2VQ80C	A1010B-2VQ80C
A1010B-1VQG80I	A1010B-1VQG80I
A1020B-VQG80C	A1020B-VQG80C
A1010B-VQ80I	A1010B-VQ80I
A1010B-2VQG80C	A1010B-2VQG80C
A10V10B-VQG80C	A10V10B-VQG80C
A1020B-1VQG80I	A1020B-1VQG80I
A1010B-1VQ80C	A1010B-1VQ80C
A1020B-1VQG80C	A1020B-1VQG80C

PDF Datasheet Preview
ACT 1 Series FPGAs • 5V and 3.3V Families fully compatible with JEDEC specifications • Up to 2000 Gate Array Gates 6000 PLD equivalent gates • Replaces up to 50 TTL Packages • Replaces up to twenty 20-Pin Packages • Design Library with over 250 Macro Functions • Gate Array Architecture Allows Completely Automatic Place and Route • Up to 547 Programmable Logic Modules • Up to 273 Flip-Flops • Data Rates to 75 MHz • Two In-Circuit Diagnostic Probe Pins Support Speed Analysis to 25 MHz • Built-In High Speed Clock Distribution Network • I/O Drive to 10 mA 5 V , 6 mA V • Nonvolatile, User Programmable • Fabricated in micron CMOS technology The ACT 1 Series of field programmable gate arrays FPGAs offers a variety of package, speed, and application combinations. Devices are implemented in silicon gate, 1-micron two-level metal CMOS, and they employ Actel’s antifuse technology. The unique architecture offers gate array flexibility, high performance, and instant turnaround through user programming. Device utilization is typically 95 to 100 percent of available logic modules. ACT 1 devices also provide system designers with unique on-chip diagnostic probe capabilities, allowing convenient testing and debugging. Additional features include an on-chip clock driver with a hardwired distribution network. The network provides efficient clock distribution with minimum skew. The user-definable I/Os are capable of driving at both TTL and CMOS drive levels. Available packages include plastic and ceramic J-leaded chip carriers, ceramic and plastic quad flatpacks, and ceramic pin grid array. Product Family Profile Device A1010B A1020B A10V10B A10V20B Capacity Gate Array Equivalent Gates PLD Equivalent Gates TTL Equivalent Packages 20-Pin PAL Equivalent Packages 1,200 3,000 30 12 2,000 6,000 50 20 Logic Modules Flip-Flops maximum Routing Resources Horizontal Tracks/Channel Vertical Tracks/Column PLICE Antifuse Elements 22 13 112,000 22 13 186,000 User I/Os maximum Packages: 44 PLCC 44 PLCC 68 PLCC 68 PLCC 84 PLCC 100 PQFP 100 PQFP 80 VQFP 80 VQFP 84 CPGA 84 CPGA 84 CQFP Performance 5 V Data Rate maximum V Data Rate maximum 75 MHz 55 MHz 75 MHz 55 MHz Note See Product Plan on page 1-286 for package availability. The Designer and Designer Advantage Systems Ordering Information ACT 1 Array Performance Temperature and Voltage Effects Worst-case delays for ACT 1 arrays are calculated in the same manner as for masked array products. A typical delay parameter is multiplied by a derating factor to account for temperature, voltage, and processing effects. However, in an ACT 1 array, temperature and voltage effects are less dramatic than with masked devices. The electrical characteristics of module interconnections on ACT 1 devices remain constant over voltage and temperature fluctuations. As a result, the total derating factor from typical to worst-case for a standard speed ACT 1 array is only to 1, compared to 2 to 1 for a masked gate array. Logic Module Size Logic module size also affects performance. A mask programmed gate array cell with four transistors usually implements only one logic level. In the more complex logic module similar to the complexity of a gate array macro of an ACT 1 array, implementation of multiple logic levels within a single module is possible. This eliminates interlevel wiring and associated RC delays. The effect is termed “net compression.” A1010 B 2 Application Temperature Range C = Commercial 0 to +70°C I = Industrial to +85°C M = Military to +125°C B = MIL-STD-883 Package Lead Count Package Type PL = Plastic J-Leaded Chip Carriers PQ = Plastic Quad Flatpacks CQ = Ceramic Quad Flatpack PG = Ceramic Pin Grid Array VQ = Very Thin Quad Flatpack Speed Grade Blank = Standard Speed = Approximately 15% faster than Standard = Approximately 25% faster than Standard = Approximately 35% faster than Standard Part Number A1010 = 1200 Gates 5 V A1020 = 2000 Gates 5 V A10V10 = 1200 Gates V A10V20 = 2000 Gates V 1-285 Product Plan Speed Grade* Application A1010B Device 44-pin Plastic Leaded Chip Carrier PL 68-pin Plastic Leaded Chip Carrier PL 100-pin Plastic Quad Flatpack PQ 80-pin Very Thin mm Quad Flatpack VQ 84-pin Ceramic Pin Grid Array PG A1020B Device 44-pin Plastic Leaded Chip Carrier PL 68-pin Plastic Leaded Chip Carrier PL 84-pin Plastic Leaded Chip Carrier PL 100-pin Plastic Quad Flatpack PQ 80-pin Very Thin mm Quad Flatpack VQ 84-pin Ceramic Pin Grid Array PG 84-pin Ceramic Quad Flatpack CQ A10V10B Device 68-pin Plastic Leaded Chip Carrier PL 80-pin Very Thin mm Quad Flatpack VQ A10V20B Device 68-pin Plastic Leaded Chip Carrier PL 84-pin Plastic Leaded Chip Carrier PL 80-pin Very Thin mm Quad Flatpack VQ Applications C = Commercial Availability = Available * Speed Grade = Approx. 15% faster than Standard I = Industrial P = Planned = Approx. 25% faster than Standard M = Military = Not Planned = Approx. 35% faster than Standard B = MIL-STD-883 Device Resources User I/Os Device A1010B, A10V10B A1020B, A10V20B Logic Modules 295 547 Gates 1200 2000 44-pin 34 68-pin 57 80-pin 57 69

PDF Datasheet Preview

ACT 1 Series FPGAs
• 5V and 3.3V Families fully compatible with JEDEC specifications
• Up to 2000 Gate Array Gates 6000 PLD equivalent gates
• Replaces up to 50 TTL Packages
• Replaces up to twenty 20-Pin Packages
• Design Library with over 250 Macro Functions
• Gate Array Architecture Allows Completely Automatic Place and Route
• Up to 547 Programmable Logic Modules
• Up to 273 Flip-Flops
• Data Rates to 75 MHz
• Two In-Circuit Diagnostic Probe Pins Support Speed Analysis to 25 MHz
• Built-In High Speed Clock Distribution Network
• I/O Drive to 10 mA 5 V , 6 mA V
• Nonvolatile, User Programmable
• Fabricated in micron CMOS technology

The ACT 1 Series of field programmable gate arrays FPGAs offers a variety of package, speed, and application combinations. Devices are implemented in silicon gate, 1-micron two-level metal CMOS, and they employ Actel’s antifuse technology. The unique architecture offers gate array flexibility, high performance, and instant turnaround through user programming. Device utilization is typically 95 to 100 percent of available logic modules.

ACT 1 devices also provide system designers with unique on-chip diagnostic probe capabilities, allowing convenient testing and debugging. Additional features include an on-chip clock driver with a hardwired distribution network. The network provides efficient clock distribution with minimum skew.

The user-definable I/Os are capable of driving at both TTL and CMOS drive levels. Available packages include plastic and ceramic J-leaded chip carriers, ceramic and plastic quad flatpacks, and ceramic pin grid array.

Product Family Profile

Device

A1010B A1020B A10V10B A10V20B

Capacity Gate Array Equivalent Gates PLD Equivalent Gates TTL Equivalent Packages 20-Pin PAL Equivalent Packages
1,200 3,000
30 12
2,000 6,000
50 20

Logic Modules

Flip-Flops maximum

Routing Resources Horizontal Tracks/Channel Vertical Tracks/Column PLICE Antifuse Elements
22 13 112,000
22 13 186,000

User I/Os maximum

Packages:
44 PLCC 44 PLCC 68 PLCC 68 PLCC
84 PLCC 100 PQFP 100 PQFP
80 VQFP 80 VQFP 84 CPGA 84 CPGA
84 CQFP

Performance 5 V Data Rate maximum V Data Rate maximum
75 MHz 55 MHz
75 MHz 55 MHz

Note See Product Plan on page 1-286 for package availability.

The Designer and Designer Advantage Systems
Ordering Information

ACT 1 Array Performance

Temperature and Voltage Effects

Worst-case delays for ACT 1 arrays are calculated in the same manner as for masked array products. A typical delay parameter is multiplied by a derating factor to account for temperature, voltage, and processing effects. However, in an ACT 1 array, temperature and voltage effects are less dramatic than with masked devices. The electrical characteristics of module interconnections on ACT 1 devices remain constant over voltage and temperature fluctuations.

As a result, the total derating factor from typical to worst-case for a standard speed ACT 1 array is only to 1, compared to 2 to 1 for a masked gate array.

Logic Module Size

Logic module size also affects performance. A mask programmed gate array cell with four transistors usually implements only one logic level. In the more complex logic module similar to the complexity of a gate array macro of an ACT 1 array, implementation of multiple logic levels within a single module is possible. This eliminates interlevel wiring and associated RC delays. The effect is termed “net compression.”

A1010 B 2

Application Temperature Range C = Commercial 0 to +70°C I = Industrial to +85°C M = Military to +125°C B = MIL-STD-883

Package Lead Count

Package Type PL = Plastic J-Leaded Chip Carriers PQ = Plastic Quad Flatpacks CQ = Ceramic Quad Flatpack PG = Ceramic Pin Grid Array VQ = Very Thin Quad Flatpack

Speed Grade Blank = Standard Speed = Approximately 15% faster than Standard = Approximately 25% faster than Standard = Approximately 35% faster than Standard

Part Number A1010 = 1200 Gates 5 V A1020 = 2000 Gates 5 V A10V10 = 1200 Gates V A10V20 = 2000 Gates V
1-285

Product Plan

Speed Grade*

Application

A1010B Device
44-pin Plastic Leaded Chip Carrier PL 68-pin Plastic Leaded Chip Carrier PL 100-pin Plastic Quad Flatpack PQ 80-pin Very Thin mm Quad Flatpack VQ 84-pin Ceramic Pin Grid Array PG

A1020B Device
44-pin Plastic Leaded Chip Carrier PL 68-pin Plastic Leaded Chip Carrier PL 84-pin Plastic Leaded Chip Carrier PL 100-pin Plastic Quad Flatpack PQ 80-pin Very Thin mm Quad Flatpack VQ 84-pin Ceramic Pin Grid Array PG 84-pin Ceramic Quad Flatpack CQ

A10V10B Device
68-pin Plastic Leaded Chip Carrier PL 80-pin Very Thin mm Quad Flatpack VQ

A10V20B Device
68-pin Plastic Leaded Chip Carrier PL 84-pin Plastic Leaded Chip Carrier PL 80-pin Very Thin mm Quad Flatpack VQ

Applications C = Commercial Availability = Available * Speed Grade = Approx. 15% faster than Standard

I = Industrial

P = Planned
= Approx. 25% faster than Standard

M = Military
= Not Planned
= Approx. 35% faster than Standard

B = MIL-STD-883

Device Resources

User I/Os

Device A1010B, A10V10B A1020B, A10V20B

Logic Modules 295 547

Gates 1200 2000
44-pin 34
68-pin 57
80-pin 57 69

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Datasheet ID: A1010B-1PLG68I 648598