MAX9450EHJ+T

MAX9450EHJ+T Datasheet

MAX9450/MAX9451/MAX9452

Part	Datasheet
MAX9450EHJ+T	MAX9450EHJ+T (pdf)

Related Parts	Information
MAX9452EHJ+	MAX9452EHJ+
MAX9451EHJ+	MAX9451EHJ+
MAX9451EHJ+T	MAX9451EHJ+T
MAX9452EHJ+T	MAX9452EHJ+T
MAX9450EHJ+	MAX9450EHJ+

PDF Datasheet Preview
High-Precision Clock Generators with Integrated VCXO MAX9450/MAX9451/MAX9452 The MAX9450/MAX9451/MAX9452 clock generators provide high-precision clocks for timing in SONET/SDH systems or Gigabit Ethernet systems. The MAX9450/ MAX9451/MAX9452 can also provide clocks for the highspeed and high-resolution ADCs and DACs in 3G base stations. Additionally, the devices can also be used as a jitter attenuator for generating high-precision CLK signals. The MAX9450/MAX9451/MAX9452 feature an integrated VCXO. This configuration eliminates the use of an external VCXO and provides a cost-effective solution for generating high-precision clocks. The MAX9450/MAX9451/ MAX9452 feature two differential inputs and clock outputs. The inputs accept LVPECL, LVDS, differential signals, and LVCMOS. The input reference clocks range from 8kHz to 500MHz. The MAX9450/MAX9451/MAX9452 offer LVPECL, HSTL, and LVDS outputs, respectively. The output range is up to 160MHz, depending on the selection of crystal. The input and output frequency selection is implemented through the I2C or SPI interface. The MAX9450/ MAX9451/MAX9452 feature clock output jitter less than 0.8ps RMS in a 12kHz to 20MHz band and phasenoise attenuation greater than -130dBc/Hz at 100kHz. The phase-locked loop PLL filter can be set externally, and the filter bandwidth can vary from 1Hz to 20kHz. The MAX9450/MAX9451/MAX9452 operate from 2.4V to 3.6V supply and are available in 32-pin TQFP packages with exposed pads. SONET/SDH Systems 10 Gigabit Network Routers and Switches 3G Cellular Phone Base Stations General Jitter Attenuation Integrated VCXO Provides a Cost-Effective Solution for High-Precision Clocks 8kHz to 500MHz Input Frequency Range 15MHz to 160MHz Output Frequency Range I2C or SPI Programming for the Input and Output Frequency Selection PLL Lock Range > ±60ppm Two Differential Outputs with Three Types of Signaling LVPECL, LVDS, or HSTL Input Clock Monitor with Hitless Switch Internal Holdover Function within ±20ppm of the Nominal Frequency Low Output CLK Jitter < 0.8ps RMS in the 12kHz to 20MHz Band Low Phase Noise > -130dBc at 100kHz, > -140dBc at 1MHz Ordering Information PART PIN-PACKAGE OUTPUT PKG CODE MAX9450EHJ 32 TQFP-EP* LVPECL H32E-6 MAX9451EHJ 32 TQFP-EP* HSTL H32E-6 MAX9452EHJ 32 TQFP-EP* LVDS H32E-6 Note All devices are specified over the -40°C to +85°C temperature range. For lead-free packages, contact factory. *EP = Exposed paddle. Pin Configuration VDDQ CLK1+ CLK1GND CLK0+ CLK0VDDQ OE TOP VIEW 24 23 22 21 20 19 18 17 VDD 25 X1 26 X2 27 VDDA 28 LP1 29 LP2 30 GNDA 31 RJ 32 MAX9450 MAX9451 MAX9452 EXPOSED PAD GND 16 CMON 15 AD1 14 AD0 13 SDA 12 SCL 11 GND/CS 10 MR 9 INT 123 45 67 8 LOCK SEL0 SEL1 IN0+ IN0VDD IN1+ IN1- SPI is a trademark of Motorola, Inc. TQFP 5mm x 5mm Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at High-Precision Clock Generators with Integrated VCXO MAX9450/MAX9451/MAX9452 ABSOLUTE MAXIMUM RATINGS VDD to GND to +4.0V VDDA to GNDA to +4.0V All Other Pins to GND ...................................-0.3V to VDD + 0.3V Short-Circuit Duration all pins Continuous Power Dissipation TA = +85°C 32-Pin TQFP derate 27.8mW/°C above +70°C ........2222mW Storage Temperature Range .............................-65°C to +165°C Maximum Junction Temperature Operating Temperature Range ...........................-40°C to +85°C Lead Temperature soldering, 10s .................................+300°C ESD Protection Human Body Model RD = 1.5kΩ, CS = 100pF ..............±2kV Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS VDDA = VDD = VDDQ = 2.4V to 3.6V, and VDDQ = 1.4V to 1.6V for MAX9451, TA = -40°C to +85°C. Typical values at VDDA = VDD = VDDQ = 3.3V, and VDDQ = 1.5V for MAX9451, TA = +25°C, unless otherwise noted. PARAMETER LVCMOS INPUT SEL_, CMON, OE, MR CONDITIONS Input High Level VIH1 Input Low Level VIL1 Input Current LVCMOS OUTPUT INT, LOCK IIN1 VIN = 0V to VDD Output High Level VOH1 IOH1 = -4mA Output Low Level THREE-LEVEL INPUT AD0, AD1 Input High Level Input Low Level Input Open Level Input Current DIFFERENTIAL INPUTS IN0, IN1 Differential Input High Threshold Differential Input Low Threshold VOL1 IOL1 = 4mA VIH2 VIL2 VIO2 IIL2, IIH2 Measured at the opened inputs VIL2 = 0V or VIH2 = VDD VIDH VIDL VID = VIN+ - VINVID = VIN+ - VIN- Common-Mode Input-Voltage Range VCOM VID = VIN+ - VIN- Input Current IIN+, IIN- MAX9450 OUTPUTS CLK0, CLK1 LVPECL Output High Voltage VOH2 50Ω load connected to VDDQ - 2.0V Output Low Voltage VOL2 50Ω load connected to VDDQ - 2.0V MAX9451 OUTPUTS CLK0, CLK1 differential HSTL Output High-Level Voltage VOH3 With 50Ω load resistor to GND, Figure 1

PDF Datasheet Preview

High-Precision Clock Generators with Integrated VCXO

MAX9450/MAX9451/MAX9452

The MAX9450/MAX9451/MAX9452 clock generators provide high-precision clocks for timing in SONET/SDH systems or Gigabit Ethernet systems. The MAX9450/ MAX9451/MAX9452 can also provide clocks for the highspeed and high-resolution ADCs and DACs in 3G base stations. Additionally, the devices can also be used as a jitter attenuator for generating high-precision CLK signals.

The MAX9450/MAX9451/MAX9452 feature an integrated VCXO. This configuration eliminates the use of an external VCXO and provides a cost-effective solution for generating high-precision clocks. The MAX9450/MAX9451/ MAX9452 feature two differential inputs and clock outputs. The inputs accept LVPECL, LVDS, differential signals, and LVCMOS. The input reference clocks range from 8kHz to 500MHz.

The MAX9450/MAX9451/MAX9452 offer LVPECL, HSTL, and LVDS outputs, respectively. The output range is up to 160MHz, depending on the selection of crystal. The input and output frequency selection is implemented through the I2C or SPI interface. The MAX9450/ MAX9451/MAX9452 feature clock output jitter less than 0.8ps RMS in a 12kHz to 20MHz band and phasenoise attenuation greater than -130dBc/Hz at 100kHz. The phase-locked loop PLL filter can be set externally, and the filter bandwidth can vary from 1Hz to 20kHz.

The MAX9450/MAX9451/MAX9452 operate from 2.4V to 3.6V supply and are available in 32-pin TQFP packages with exposed pads.

SONET/SDH Systems
10 Gigabit Network Routers and Switches
3G Cellular Phone Base Stations

General Jitter Attenuation

Integrated VCXO Provides a Cost-Effective Solution for High-Precision Clocks
8kHz to 500MHz Input Frequency Range
15MHz to 160MHz Output Frequency Range I2C or SPI Programming for the Input and Output

Frequency Selection

PLL Lock Range > ±60ppm

Two Differential Outputs with Three Types of Signaling LVPECL, LVDS, or HSTL

Input Clock Monitor with Hitless Switch

Internal Holdover Function within ±20ppm of the Nominal Frequency

Low Output CLK Jitter < 0.8ps RMS in the 12kHz to 20MHz Band

Low Phase Noise > -130dBc at 100kHz, > -140dBc at 1MHz
Ordering Information

PART

PIN-PACKAGE OUTPUT PKG CODE

MAX9450EHJ 32 TQFP-EP*

LVPECL

H32E-6

MAX9451EHJ 32 TQFP-EP*

HSTL

H32E-6

MAX9452EHJ 32 TQFP-EP*

LVDS

H32E-6

Note All devices are specified over the -40°C to +85°C temperature range.

For lead-free packages, contact factory. *EP = Exposed paddle.

Pin Configuration

VDDQ CLK1+ CLK1GND CLK0+ CLK0VDDQ OE

TOP VIEW
24 23 22 21 20 19 18 17

VDD 25 X1 26 X2 27 VDDA 28 LP1 29 LP2 30 GNDA 31 RJ 32

MAX9450 MAX9451 MAX9452

EXPOSED PAD GND
16 CMON 15 AD1 14 AD0 13 SDA 12 SCL 11 GND/CS 10 MR 9 INT
123 45 67 8

LOCK SEL0 SEL1 IN0+ IN0VDD IN1+ IN1-

SPI is a trademark of Motorola, Inc.

TQFP 5mm x 5mm

Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at

High-Precision Clock Generators with Integrated VCXO

MAX9450/MAX9451/MAX9452

ABSOLUTE MAXIMUM RATINGS

VDD to GND to +4.0V VDDA to GNDA to +4.0V All Other Pins to GND ...................................-0.3V to VDD + 0.3V Short-Circuit Duration all pins

Continuous Power Dissipation TA = +85°C 32-Pin TQFP derate 27.8mW/°C above +70°C ........2222mW

Storage Temperature Range .............................-65°C to +165°C Maximum Junction Temperature Operating Temperature Range ...........................-40°C to +85°C Lead Temperature soldering, 10s .................................+300°C ESD Protection

Human Body Model RD = 1.5kΩ, CS = 100pF ..............±2kV

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

DC ELECTRICAL CHARACTERISTICS

VDDA = VDD = VDDQ = 2.4V to 3.6V, and VDDQ = 1.4V to 1.6V for MAX9451, TA = -40°C to +85°C. Typical values at VDDA = VDD = VDDQ = 3.3V, and VDDQ = 1.5V for MAX9451, TA = +25°C, unless otherwise noted.

PARAMETER

LVCMOS INPUT SEL_, CMON, OE, MR

CONDITIONS

Input High Level

VIH1

Input Low Level

VIL1

Input Current LVCMOS OUTPUT INT, LOCK

IIN1

VIN = 0V to VDD

Output High Level

VOH1 IOH1 = -4mA

Output Low Level THREE-LEVEL INPUT AD0, AD1 Input High Level Input Low Level Input Open Level Input Current DIFFERENTIAL INPUTS IN0, IN1 Differential Input High Threshold Differential Input Low Threshold

VOL1 IOL1 = 4mA

VIH2 VIL2 VIO2 IIL2, IIH2

Measured at the opened inputs VIL2 = 0V or VIH2 = VDD

VIDH VIDL

VID = VIN+ - VINVID = VIN+ - VIN-

Common-Mode Input-Voltage Range

VCOM VID = VIN+ - VIN-

Input Current

IIN+, IIN-

MAX9450 OUTPUTS CLK0, CLK1 LVPECL

Output High Voltage

VOH2 50Ω load connected to VDDQ - 2.0V

Output Low Voltage

VOL2 50Ω load connected to VDDQ - 2.0V

MAX9451 OUTPUTS CLK0, CLK1 differential HSTL

Output High-Level Voltage

VOH3 With 50Ω load resistor to GND, Figure 1

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Datasheet ID: MAX9450EHJ+T 647423