MAX3637ETM+T

MAX3637ETM+T Datasheet

MAX3637

Part	Datasheet
MAX3637ETM+T	MAX3637ETM+T (pdf)

Related Parts	Information
MAX3637ETM+	MAX3637ETM+

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MAX3637 EVAALVUAAILTAIOBNLEKIT Low-Jitter, Wide Frequency Range, Programmable Clock Generator with 10 Outputs The MAX3637 is a highly flexible, precision phaselocked loop PLL clock generator optimized for the next generation of network equipment that demands low-jitter clock generation and distribution for robust high-speed data transmission. The device features subpicosecond jitter generation, excellent power-supply noise rejection, and pin-programmable LVDS/LVPECL output interfaces. The MAX3637 provides nine differential outputs and one LVCMOS output, divided into three banks. The frequency and output interface of each output bank can be individually programmed, making this device an ideal replacement for multiple crystal oscillators and clock distribution ICs on a system board, saving cost and space. This 3.3V IC is available in a 7mm x 7mm, 48-pin TQFN package and operates from -40°C to +85°C. Ethernet Switch/Router Wireless Base Station Fibre Channel SAN SONET Line Cards Typical Application Circuits and Pin Configuration appear at end of data sheet. S Inputs Crystal Interface 18MHz to 33.5MHz LVCMOS Input 15MHz to 160MHz Differential Input 15MHz to 350MHz S Outputs LVCMOS Output Up to 160MHz LVPECL/LVDS Outputs Up to 800MHz S Three Individual Output Banks Pin-Programmable Dividers Pin-Programmable Output Interface S Wide VCO Tuning Range 3.60GHz to 3.83GHz S Low Phase Jitter 0.34psRMS 12kHz to 20MHz 0.14psRMS 1.875MHz to 20MHz S Excellent Power-Supply Noise Rejection S -40NC to +85NC Operating Temperature Range S +3.3V Supply Ordering Information PART MAX3637ETM+ TEMP RANGE -40NC to +85NC PIN-PACKAGE 48 TQFN-EP* +Denotes a lead Pb -free/RoHS-compliant package. *EP = Exposed pad. Functional Diagram XOUT XIN CIN XO LVCMOS MAX3637 PLL, DIVIDERS, MUXES VCO LVPECL/LVDS LVPECL/LVDS LVPECL/LVDS LVPECL/LVDS LVPECL/LVDS LVPECL/LVDS LVPECL/LVDS LVPECL/LVDS LVPECL/LVDS LVCMOS Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at MAX3637 Low-Jitter, Wide Frequency Range, Programmable Clock Generator with 10 Outputs ABSOLUTE MAXIMUM RATINGS Supply Voltage Range VCC, VCCA, VCCQA, VCCQB, VCCQC, to +4.0V Voltage Range at CIN, IN_SEL, DM, DF[1:0], DP, PLL_BP, DA[1:0], DB[1:0], DC[1:0], QA_CTRL1, QA_CTRL2, QB_CTRL, QC_CTRL, QCC, RES............................ -0.3V to VCC + 0.3V Voltage Range at DIN, DIN......... VCC - 2.35V to VCC - 0.35V Voltage Range at QA[4:0], QA[4:0], QB[2:0], QB[2:0], QC, QC when LVDS Output... -0.3V to VCC + 0.3V Current into QA[4:0], QA[4:0], QB[2:0], QB[2:0], QC, QC when LVPECL -56mA Current into Q50mA Voltage Range at to +1.2V Voltage Range at XOUT.............................-0.3V to VCC - 0.6V Continuous Power Dissipation TA = +70NC 48-Pin TQFN derate 40mW/NC above +70NC ..........3200mW Operating Junction Temperature Range.......... -55NC to +150NC Storage Temperature Range............................ -65NC to +160NC Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS VCC = +3.0V to +3.6V, TA = -40°C to +85°C. Typical values are at VCC = +3.3V, TA = +25°C, unless otherwise noted. Signal applied to CIN or DIN/DIN only when selected as the reference clock. Note 1 PARAMETER CONDITIONS MIN TYP MAX Supply Current with PLL Enabled Note 2 Configured with LVPECL outputs Configured with LVDS outputs 170 215 290 365 Supply Current with PLL Bypassed Note 2 Configured with LVPECL outputs Configured with LVDS outputs LVCMOS/LVTTL CONTROL INPUTS IN_SEL, DM, DF[1:0], DA[1:0], DB[1:0], DC[1:0], PLL_BP, DP, QA_CTRL1, QA_CTRL2, QB_CTRL, QC_CTRL Input High Voltage Input Low Voltage Input High Current Input Low Current LVCMOS/LVTTL CLOCK INPUT CIN VIN = VCC VIN = 0V Reference Clock Input Frequency fREF UNITS mA Input Amplitude Range Internally AC-coupled Note 3 Input High Current Input Low Current Reference Clock Input DutyCycle Distortion VIN = VCC

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MAX3637

EVAALVUAAILTAIOBNLEKIT

Low-Jitter, Wide Frequency Range,

Programmable Clock Generator with 10 Outputs

The MAX3637 is a highly flexible, precision phaselocked loop PLL clock generator optimized for the next generation of network equipment that demands low-jitter clock generation and distribution for robust high-speed data transmission. The device features subpicosecond jitter generation, excellent power-supply noise rejection, and pin-programmable LVDS/LVPECL output interfaces. The MAX3637 provides nine differential outputs and one LVCMOS output, divided into three banks. The frequency and output interface of each output bank can be individually programmed, making this device an ideal replacement for multiple crystal oscillators and clock distribution ICs on a system board, saving cost and space.

This 3.3V IC is available in a 7mm x 7mm, 48-pin TQFN package and operates from -40°C to +85°C.

Ethernet Switch/Router Wireless Base Station

Fibre Channel SAN SONET Line Cards

Typical Application Circuits and Pin Configuration appear at end of data sheet.

S Inputs Crystal Interface 18MHz to 33.5MHz LVCMOS Input 15MHz to 160MHz Differential Input 15MHz to 350MHz

S Outputs LVCMOS Output Up to 160MHz LVPECL/LVDS Outputs Up to 800MHz

S Three Individual Output Banks Pin-Programmable Dividers Pin-Programmable Output Interface

S Wide VCO Tuning Range 3.60GHz to 3.83GHz

S Low Phase Jitter 0.34psRMS 12kHz to 20MHz 0.14psRMS 1.875MHz to 20MHz

S Excellent Power-Supply Noise Rejection

S -40NC to +85NC Operating Temperature Range

S +3.3V Supply
Ordering Information

PART MAX3637ETM+

TEMP RANGE -40NC to +85NC

PIN-PACKAGE 48 TQFN-EP*
+Denotes a lead Pb -free/RoHS-compliant package. *EP = Exposed pad.

Functional Diagram

XOUT XIN CIN

XO LVCMOS

MAX3637

PLL, DIVIDERS, MUXES VCO

LVPECL/LVDS

LVPECL/LVDS

LVPECL/LVDS

LVPECL/LVDS

LVPECL/LVDS

LVPECL/LVDS

LVPECL/LVDS

LVPECL/LVDS

LVPECL/LVDS

LVCMOS

Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at

MAX3637

Low-Jitter, Wide Frequency Range, Programmable Clock Generator with 10 Outputs

ABSOLUTE MAXIMUM RATINGS

Supply Voltage Range VCC, VCCA, VCCQA, VCCQB, VCCQC, to +4.0V

Voltage Range at CIN, IN_SEL, DM, DF[1:0],

DP, PLL_BP, DA[1:0], DB[1:0], DC[1:0],

QA_CTRL1, QA_CTRL2, QB_CTRL,

QC_CTRL, QCC, RES............................ -0.3V to VCC + 0.3V Voltage Range at DIN, DIN......... VCC - 2.35V to VCC - 0.35V Voltage Range at QA[4:0], QA[4:0], QB[2:0],

QB[2:0], QC, QC when LVDS Output... -0.3V to VCC + 0.3V

Current into QA[4:0], QA[4:0], QB[2:0], QB[2:0], QC, QC when LVPECL -56mA

Current into Q50mA Voltage Range at to +1.2V Voltage Range at XOUT.............................-0.3V to VCC - 0.6V Continuous Power Dissipation TA = +70NC
48-Pin TQFN derate 40mW/NC above +70NC ..........3200mW Operating Junction Temperature Range.......... -55NC to +150NC Storage Temperature Range............................ -65NC to +160NC

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

VCC = +3.0V to +3.6V, TA = -40°C to +85°C. Typical values are at VCC = +3.3V, TA = +25°C, unless otherwise noted. Signal applied to CIN or DIN/DIN only when selected as the reference clock. Note 1

PARAMETER

CONDITIONS

MIN TYP MAX

Supply Current with PLL Enabled Note 2

Configured with LVPECL outputs

Configured with LVDS outputs
170 215 290 365

Supply Current with PLL Bypassed Note 2

Configured with LVPECL outputs

Configured with LVDS outputs

LVCMOS/LVTTL CONTROL INPUTS IN_SEL, DM, DF[1:0], DA[1:0], DB[1:0], DC[1:0], PLL_BP, DP, QA_CTRL1, QA_CTRL2, QB_CTRL, QC_CTRL

Input High Voltage

Input Low Voltage

Input High Current

Input Low Current

LVCMOS/LVTTL CLOCK INPUT CIN

VIN = VCC VIN = 0V

Reference Clock Input Frequency
fREF

UNITS mA

Input Amplitude Range

Internally AC-coupled Note 3

Input High Current Input Low Current

Reference Clock Input DutyCycle Distortion

VIN = VCC

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Datasheet ID: MAX3637ETM+T 647311