Evaluates MAX3624
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MAX3624EVKIT+ (pdf) |
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Evaluates MAX3624 MAX3624 Evaluation Kit The MAX3624 evaluation kit EV kit is an assembled demonstration board that provides convenient evaluation of the MAX3624 low-jitter, precision clock generator. The EV kit includes an on-board 25MHz crystal to allow immediate testing. The EV kit includes switches to allow easy selection of different modes of operation. The reference input and clock outputs use SMA connectors and are AC-coupled to simplify connection to test equipment. PART MAX3624EVKIT Ordering Information TEMP RANGE 0°C to +85°C IC PACKAGE 32 TQFP-EP AC-Coupled I/Os for Ease of Testing Fully Assembled and Tested +3.3V Power-Supply Operation On-Board 25MHz Crystal SUPPLIER NDK Part Suppliers WEBSITE DESIGNATION QTY C1, C3, C4, C5, C19, 0.1uF ±10% ceramic capacitors 0402 1 10uF ±10% ceramic capacitor 0603 0.01uF ±10% ceramic capacitors 0402 27pF ±10% ceramic capacitor 0402 1 33pF ±10% ceramic capacitor 0402 J1, J3, J5 J2, J48 J4 J18, J19, J36, J43 1 4.7pF ±10% ceramic capacitor 0402 0 Not installed 2 Test points 1 2-pin header, 0.1in centers 8 SMA connectors Component List DESIGNATION L1 R7 R6, R8, R9 R42 R57 R59 R61 SW11 QTY 1 6 0 1 DESCRIPTION 2.7uH inductor ±5% resistors 0402 Not installed ±1% resistor 0402 ±1% resistor 0402 ±1% resistor 0402 ±5% resistor 0402 SP3T switches SW4, SW12, SW13, 8 SPDT switches SW15 TP6, TP7 U1 2 Test points 1 MAX3624UTJ+ None 25MHz crystal NDK EXS00A-AT00429 1 Shunt Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at Evaluates MAX3624 MAX3624 Evaluation Kit Quick Start For evaluation of the MAX3624, configure the EV kit as follows: 1 Determine which output is going to be evaluated and connect to the test equipment through SMA cables. Be sure not to leave any outputs unterminated, i.e., place 50Ω terminators on all unused outputs. 2 Connect a +3.3V power supply to J48 VCC and J2 GND . Set the current limit to 200mA. 3 If the on-board crystal is used IN_SEL set high , the PLL divider should be set to divide by 25 FB_SEL1 and FB_SEL0 set low to achieve the standard output rates shown in Table 4 Use Table 3 to set the output divider switches to achieve the output frequency desired. 5 Enable the output under test by setting the related output-enable switch, Qx_OE, high. Table Adjustment and Control Descriptions see Quick Start first COMPONENT SW1 SW2 SW3 SW4 SW7 SW8 SW9 SW11 SW12 SW13 SW15 NAME INDUCTOR SHUNT SELB1 SELB0 SELA1 QAC_OE BYPASS FB_SEL1 FB_SEL0 QA_OE SELA0 QB1_OE IN_SEL QB0_OE FUNCTION J4 shunts the power-supply inductor. Normal operation is J4 shunted. SW1 and SW2 set the output divider for the QB outputs. See Table 2 for more information. SW1 and SW2 set the output divider for the QB outputs. See Table 2 for more information. SW3 and SW11 set the output divider for the QA outputs. See Table 2 for more information. Set high to enable the LVCMOS output, QA_C. Set low to disable QA_C. Set low to bypass the PLL. Set high to engage the PLL. Note that when the PLL is bypassed, the output dividers are automatically set to divide by SW7 and SW8 set the PLL divider. See Table 3 for more information. SW7 and SW8 set the PLL divider. See Table 3 for more information. Set high to enable LVPECL output QA. Set low to force a logic zero at QA. SW3 and SW11 set the output divider for the QA outputs. See Table 2 for more information. Set high to enable LVPECL output QB1. Set low to force a logic zero at QB1. Set high to select the crystal as the frequency source. Set low to select the REF_IN as the frequency source. Set high to enable LVPECL output QB0. Set low to force a logic zero at QB0. Evaluates MAX3624 Table PLL Divider Settings FB_SEL1 LOW HIGH INPUT FB_SEL0 LOW HIGH LOW HIGH M DIVIDER ÷25 ÷24 ÷32 ÷16 MAX3624 Evaluation Kit Table Output Divider Settings INPUT NA/NB DIVIDER OUTPUT FREQUENCY SELA1/SELB1 SELA0/SELB0 M = 25 AND XTAL = 25MHz |
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