VSC3144
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VSC3144XHR-02 (pdf) |
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VSC3144HR-02 |
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VSC3144XHR-12 |
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VSC3144XHR-32 |
PDF Datasheet Preview |
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VSC3144 Gbps 144 x 144 Asynchronous Crosspoint Switch The fully non-blocking switch core of the VSC3144 device is programmed using a multimode port interface that allows random access programming of each I/O port. Each VSC3144 data output can be programmed to connect to any of its inputs. The signal path through the device uses no registers and is fully asynchronous. This means there are no restrictions on the phase, frequency, or signal pattern of any input. A high degree of signal integrity is maintained throughout the VSC3144 device because each high-speed output is a fully differential, switchedcurrent driver with on-die terminations. Data inputs are terminated on-die using 100 Ω resistors between true and complement inputs, with a common connection to an internal bias source, which facilitates AC coupling to the switch inputs. Core programming for the VSC3144 device can be sequential on a port-by-port basis, or multiple program assignments can be queued and issued simultaneously using the CONFIG bit. The entire device can be initialized for straight-through, multicast, or other configurations. Unused channels can be powered down to allow efficient use of the switch in applications that require only a subset of the available I/O channels. Power-down is enabled in the software by programming individual unused outputs with a power-down code. • Core and Metro transport • Enterprise • High-speed automated test equipment • Broadcast video systems • Storage, Ethernet, and networking equipment SPECIFICATIONS • Gbps NRZ per-channel data rate • V power supply V or V program port power supply • V or V CMOS TTL-compatible I/O • Differential CML I/O with integrated termination impedance • 0 °C to 85 °C operating temperature range Backplane Application: Line Cards FPGA/ ASIC Central Switch VSC3144 Making next-generation networks a reality. VSC3144 • Gbps 144 x 144 strictly non-blocking switch matrix with multicast and output striping programming modes • Input signal equalization ISE with programmable control globally or on a per-channel basis • Adjustable output pre-emphasis EQ • Differential current mode logic CML data output driver • Protocol-independent switching and data transmission • 16 W typical power dissipation • 45 mm x 45 mm, mm pin pitch, 1072-pin BGA package • Parallel and serial programming modes for configuration and monitoring • Software control to optimize power dissipation VSC3144 Block Diagram: Switch Core Inputs [143:0] Outputs [143:0] Bene ts • 936 Gbps aggregate bandwidth in a single chip for high-density network switching and video systems • Addresses system-level and board-level signal integrity SI and intersymbol interface ISI jitter issues • EQ and drive flexibility for driving boards, cables, and circuit traces • Convenient I/O flexibility for interfacing with multiple standards • Can be used with latest storage, Ethernet, and networking standards • Low per-channel power • Layout-friendly package and pinout for easier PCB design • Programming and control convenience • Control and lower overall power when ports are not in use Related Vitesse Products Visit for information about other related Vitesse products. |
More datasheets: 7134SA35P | 7134SA20P | 7134LA70P | 7134LA45P | 7134LA35P | 7134LA25P | 7134LA20P | 7134LA55P | DFG-30445-000 | VSC3144HR-02 |
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