RC28F256P30B85A

RC28F256P30B85A Datasheet

TE28F640P30B85 TE28F640P30T85 JS28F640P30B85 JS28F640P30T85 RC28F640P30B85 RC28F640P30T85 PC28F640P30B85 PC28F640P30T85

Part	Datasheet
RC28F256P30B85A	RC28F256P30B85A (pdf)

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PF48F3000P0ZTQ0A	PF48F3000P0ZTQ0A
TE28F256P30B95A	TE28F256P30B95A
RC28F128P30B85A	RC28F128P30B85A
RC28F256P30T85A	RC28F256P30T85A
PC28F256P30B85F	PC28F256P30B85F
TE28F256P30T95A	TE28F256P30T95A
RC48F4400P0VB00A	RC48F4400P0VB00A
PC28F128P30B85E	PC28F128P30B85E
PC28F640P30B85E	PC28F640P30B85E
RC28F128P30T85A	RC28F128P30T85A
PC48F4400P0VB00A	PC48F4400P0VB00A
PC28F256P30B85D TR	PC28F256P30B85D TR
JS28F256P30B95B TR	JS28F256P30B95B TR
PC28F128P30T85B TR	PC28F128P30T85B TR
PC28F640P30B85D TR	PC28F640P30B85D TR
PC48F4400P0VB00B TR	PC48F4400P0VB00B TR
RC28F640P30T85A	RC28F640P30T85A
RC28F640P30B85A	RC28F640P30B85A
PF48F3000P0ZBQ0A	PF48F3000P0ZBQ0A
PF48F4000P0ZTQ0A	PF48F4000P0ZTQ0A
PC28F640P30T85B TR	PC28F640P30T85B TR
RD48F4000P0ZBQ0A	RD48F4000P0ZBQ0A
PF48F4000P0ZBQ0A	PF48F4000P0ZBQ0A
RC28F640P30B85B TR	RC28F640P30B85B TR
RC28F256P30B85D TR	RC28F256P30B85D TR
TE48F4400P0TB00A	TE48F4400P0TB00A
PF48F4400P0VBQ0A	PF48F4400P0VBQ0A
PC28F256P30T85B TR	PC28F256P30T85B TR
RD48F4400P0VBQ0A	RD48F4400P0VBQ0A
TE48F4400P0VB00A	TE48F4400P0VB00A
PF48F2000P0ZBQ0A	PF48F2000P0ZBQ0A
PF48F2000P0ZTQ0A	PF48F2000P0ZTQ0A
RC28F256P30T85B TR	RC28F256P30T85B TR
RC48F4400P0TB00A	RC48F4400P0TB00A
PC28F128P30B85D TR	PC28F128P30B85D TR
TE28F128P30B85A	TE28F128P30B85A
RD48F3000P0ZBQ0A	RD48F3000P0ZBQ0A
TE28F128P30T85A	TE28F128P30T85A
TE28F640P30B85A	TE28F640P30B85A
RD48F3000P0ZTQ0A	RD48F3000P0ZTQ0A
TE28F640P30T85A	TE28F640P30T85A
JS48F4400P0TB00A	JS48F4400P0TB00A
JS48F4400P0VB00A	JS48F4400P0VB00A
RD48F2000P0ZBQ0A	RD48F2000P0ZBQ0A
PC48F4400P0VB02E	PC48F4400P0VB02E
PC48F4400P0VB02F TR	PC48F4400P0VB02F TR
PC48F4400P0VB0EF TR	PC48F4400P0VB0EF TR
TE28F256P30BFA	TE28F256P30BFA
TE28F256P30TFA	TE28F256P30TFA
JS28F256P30T95A	JS28F256P30T95A
PC28F640P30T85A	PC28F640P30T85A
PC28F128P30B85A	PC28F128P30B85A
PC28F640P30B85A	PC28F640P30B85A
PC28F128P30T85A	PC28F128P30T85A
PC28F256P30T85A	PC28F256P30T85A
JS28F256P30B95A	JS28F256P30B95A
JS28F128P30T85A	JS28F128P30T85A
JS28F128P30B85A	JS28F128P30B85A
JS28F640P30T85A	JS28F640P30T85A
JS28F640P30B85A	JS28F640P30B85A
PC28F256P30B85A	PC28F256P30B85A

PDF Datasheet Preview
Numonyx StrataFlash Embedded Memory P30 Product Features Datasheet - High performance - Security 85 ns initial access One-Time Programmable Registers: 52 MHz with zero wait states, 17ns clock-to-data output • 64 unique factory device identifier bits synchronous-burst read mode • 2112 user-programmable OTP bits 25 ns asynchronous-page read mode Selectable OTP Space in Main Array: 4-, 8-, 16-, and continuous-word burst mode • Four pre-defined 128-KByte blocks top or bottom Buffered Enhanced Factory Programming BEFP at 5 us/ configuration byte Typ • Up to Full Array OTP Lockout V buffered programming at 7 us/byte Typ Absolute write protection VPP = VSS - Architecture Power-transition erase/program lockout Individual zero-latency block locking Multi-Level Cell Technology Highest Density at Lowest Individual block lock-down Cost Asymmetrically-blocked architecture - Software Four 32-KByte parameter blocks top or bottom 20 us Typ program suspend configuration 20 us Typ erase suspend 128-KByte main blocks Numonyx Flash Data Integrator optimized - Voltage and Power VCC core voltage V VCCQ I/O voltage V Standby current 20uA Typ for 64-Mbit Basic Command Set and Extended Command Set compatible Common Flash Interface capable - Density and Packaging 4-Word synchronous read current: 56- Lead TSOP package 64, 128, 256, 13 mA Typ at 40 MHz Ordering Information Discrete SCSP A Supplemental Reference B Conventions - Additional Information Datasheet 4 August 2008 306666-12 Functional Description Introduction This document provides information about the Numonyx Embedded Memory P30 product and describes its features, operation, and specifications. The Numonyx Embedded Memory P30 product is the latest generation of Numonyx memory devices. Offered in 64-Mbit up through 512-Mbit densities, the P30 device brings reliable, two-bit-per-cell storage technology to the embedded flash market segment. Benefits include more density in less space, highspeed interface, lowest cost-per-bit NOR device, and support for code and data storage. Features include high-performance synchronous-burst read mode, fast asynchronous access times, low power, flexible security options, and three industry standard package choices. The P30 product family is manufactured using Intel* 130 nm ETOX VIII process technology. The P30 product family is also planned on the Intel* 65nm process lithography. 65nm AC timing changes are noted in this datasheet, and should be taken into account for all new designs. Overview This section provides an overview of the features and capabilities of the P30. The P30 family provides density upgrades from 64-Mbit through 512-Mbit. This family of devices provides high performance at low voltage on a 16-bit data bus. Individually erasable memory blocks are sized for optimum code and data storage. Upon initial power up or return from reset, the device defaults to asynchronous pagemode read. Configuring the Read Configuration Register enables synchronous burstmode reads. In synchronous burst mode, output data is synchronized with a usersupplied clock signal. A WAIT signal provides an easy CPU-to-flash memory synchronization. In addition to the enhanced architecture and interface, the device incorporates technology that enables fast factory program and erase operations. Designed for lowvoltage systems, the P30 supports read operations with VCC at V, and erase and program operations with VPP at V or V. Buffered Enhanced Factory Programming BEFP provides the fastest flash array programming performance with VPP at V, which increases factory throughput. With VPP at V, VCC and VPP can be tied together for a simple, ultra low power design. In addition to voltage flexibility, a dedicated VPP connection provides complete data protection when VPP VPPLK. A Command User Interface CUI is the interface between the system processor and all internal operations of the device. An internal Write State Machine WSM automatically executes the algorithms and timings necessary for block erase and program. A Status Register indicates erase or program completion and any errors that may have occurred. An industry-standard command sequence invokes program and erase automation. Each erase operation erases one block. The Erase Suspend feature allows system software to pause an erase cycle to read or program data in another block. Program Suspend allows system software to pause programming to read other locations. Data is programmed in word increments 16 bits . August 2008 Order Number 306666-12 Datasheet 5 The P30 protection register allows unique flash device identification that can be used to increase system security. The individual Block Lock feature provides zero-latency block locking and unlocking. In addition, the P30 device also has four pre-defined spaces in the main array that can be configured as One-Time Programmable OTP . Virtual Chip Enable Description The P30 512Mbit devices employ a Virtual Chip Enable which combines two 256-Mbit die with a common chip enable, F1-CE# for QUAD+ packages or CE# for Easy BGA and TSOP packages. Refer to Figure 9 on page 21 and Figure 10 on page Address A24 Quad+ package or A25 Easy BGA and TSOP packages is then used to select between the die pair with F1-CE# / CE# asserted depending upon the package option used. When chip enable is asserted and QUAD+ A24 Easy BGA/TSOP A25 is low VIL , The lower parameter die is selected when chip enable is asserted and QUAD+ A24 Easy BGA/TSOP A25 is high VIH , the upper parameter die is selected. Refer to Table 1 and Table 2 for additional details. Table 1 Virtual Chip Enable Truth Table for 512 Mb QUAD+ Package Lower Param Die Upper Param Die Die Selected F1-CE# L A24 L H Table 2 Virtual Chip Enable Truth Table for 512 Mb Easy BGA & TSOP Packages Lower Param Die Upper Param Die Die Selected CE# L A25 L H Datasheet 6 August 2008 306666-12 Memory Maps Table 3 through Table 5 show the P30 memory maps. The memory array is divided into multiple 8-Mbit Programming Regions see Section “Program Operation” on page Table 3 Discrete Top Parameter Memory Maps all packages Size 64-Mbit 3FC000 - Size On e Programming Table 22 Burst Sequence Word Ordering Start Addr. DEC Burst Wrap RCR[3] 4-Word Burst BL[2:0] = 0b001 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 Burst Addressing Sequence DEC 8-Word Burst BL[2:0] = 0b010 16-Word Burst BL[2:0] = 0b011 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 Continuous Burst BL[2:0] = 0b111 0-1-2-3 1-2-3-4 2-3-4-5 3-4-5-6 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-8 2-3-4-5-6-7-8-9 3-4-5-6-7-8-9-10 4-5-6-7-8-9-10-11 5-6-7-8-9-10-11-12 6-7-8-9-10-11-12-13 7-8-9-10-11-12-13- 14 15 Clock Edge The Clock Edge CE bit selects either a rising default or falling clock edge for CLK. This clock edge is used at the start of a burst cycle, to output synchronous data, and to assert/deassert WAIT. Datasheet 46 August 2008 306666-12 Burst Wrap The Burst Wrap BW bit determines whether 4-word, 8-word, or 16-word burst length accesses wrap within the selected word-length boundaries or cross word-length boundaries. When BW is set, burst wrapping does not occur default . When BW is cleared, burst wrapping occurs. When performing synchronous burst reads with BW set no wrap , an output delay may occur when the burst sequence crosses its first device-row 16-word boundary. If the burst sequence’s start address is 4-word aligned, then no delay occurs. If the start address is at the end of a 4-word boundary, the worst case output delay is one clock cycle less than the first access Latency Count. This delay can take place only once, and doesn’t occur if the burst sequence does not cross a device-row boundary. WAIT informs the system of this delay when it occurs. Burst Length The Burst Length bit BL[2:0] selects the linear burst length for all synchronous burst reads of the flash memory array. The burst lengths are 4-word, 8-word, 16-word, and continuous word. Continuous-burst accesses are linear only, and do not wrap within any word length boundaries see Table 22, “Burst Sequence Word Ordering” on page When a burst cycle begins, the device outputs synchronous burst data until it reaches the end of the “burstable” address space. End of Word Line EOWL Considerations When performing synchronous burst reads with BW set no wrap and DH reset 1 clock cycle , an output “delay” requiring additions clock Wait States may occur when the burst sequence crosses its first device-row 16-word boundary. The delay would take place only once, and will not occur if the burst sequence does not cross a device-row boundary. The WAIT signal informs the system of this delay when it occurs. If the burst sequence’s start address is 4-word aligned i.e. 0x00h, 0x04h, 0x08h, 0x0Ch then no delay occurs. If the start address is at the end of a 4-word boundary i.e. 0x03h, 0x07h, 0x0Bh, 0x0Fh , the worst case delay number of Wait States required will be one clock cycle less than the first access Latency Count LC-1 when crossing the first device-row boundary i.e. 0x0Fh to 0x10h . Other address misalignments may require wait states depending upon the LC setting and the starting address alignment. For example, an LC setting of 3 with a starting address of 0xFD requires 0 wait states, but the same LC setting of 3 with a starting address of 0xFE would require 1 wait state when crossing the first device row boundary. One-Time-Programmable OTP Registers The device contains 17 one-time-programmable OTP registers that can be used to implement system security measures and/or device identification. Each OTP register can be individually locked. The first 128-bit OTP Register is comprised of two 64-bit 8-word segments. The lower 64-bit segment is pre-programmed at the Numonyx factory with a unique 64-bit number. The other 64-bit segment, as well as the other sixteen 128-bit OTP Registers, are blank. Users can program these registers as needed. When programmed, users can then lock the OTP Register s to prevent additional bit programming see Figure 16, “OTP register map” on page The OTP Registers contain one-time programmable OTP bits when programmed, PR bits cannot be erased. Each OTP Register can be accessed multiple times to program individual bits, as long as the register remains unlocked. August 2008 Order Number 306666-12 Datasheet 47 Each OTP Register has an associated Lock Register bit. When a Lock Register bit is programmed, the associated OTP Register can only be read it can no longer be programmed. Additionally, because the Lock Register bits themselves are OTP, when programmed, Lock Register bits cannot be erased. Therefore, when a OTP Register is locked, it cannot be unlocked. Figure 16 OTP register map 0x109 128-bit Protection Register 16 User-Programmable 0x102 0x91 128-bit Protection Register 1 User-Programmable 0x8A Lock Register 1 0x89 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x88 0x85 0x84 0x81 64-bit Segment User-Programmable 128-Bit Protection Register 0 64-bit Segment Factory-Programmed Lock Register 0 0x80 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reading the OTP registers The OTP registers can be read from any address. To read the OTP Register, first issue the Read Device Identifier command at any address to place the device in the Read Device Identifier state see Section “Command Set” on page Next, perform a read operation using the address offset corresponding to the register to be read. Table 13, “Device Identifier Information” on page 28 shows the address offsets of the OTP Registers and Lock Registers. PR data is read 16 bits at a time. Datasheet 48 August 2008 306666-12 Note: Caution: Programming the OTP Registers To program any of the OTP Registers, first issue the Program OTP Register command at the parameter’s base address plus the offset to the desired OTP Register see Section “Command Set” on page Next, write the desired OTP Register data to the same OTP Register address see Figure 16, “OTP register map” on page The device programs the 64-bit and 128-bit user-programmable OTP Register data 16 bits at a time see Figure 41, “Protection Register Programming Flowchart” on page Issuing the Program OTP Register command outside of the OTP Register’s address space causes a program error SR[4] set . Attempting to program a locked OTP Register causes a program error SR[4] set and a lock error SR[1] set . When programming the OTP bits in the OTP registers for a Top Parameter Device, the following upper address bits must also be driven properly A[Max:17] driven high VIH for TSOP and Easy BGA packages, and A[Max:16] driven high VIH for QUAD+ SCSP. Locking the OTP Registers Each OTP Register can be locked by programming its respective lock bit in the Lock Register. To lock a OTP Register, program the corresponding bit in the Lock Register by issuing the Program Lock Register command, followed by the desired Lock Register data see Section “Command Set” on page The physical addresses of the Lock Registers are 0x80 for register 0 and 0x89 for register These addresses are used when programming the lock registers see Table 13, “Device Identifier Information” on page Bit 0 of Lock Register 0 is already programmed during the manufacturing process at the “factory”, locking the lower, pre-programmed 64-bit region of the first 128-bit OTP Register containing the unique identification number of the device. Bit 1 of Lock Register 0 can be programmed by the user to lock the user-programmable, 64-bit region of the first 128-bit OTP Register. When programming Bit 1 of Lock Register 0, all other bits need to be left as ‘1’ such that the data programmed is 0xFFFD. Lock Register 1 controls the locking of the upper sixteen 128-bit OTP Registers. Each of the 16 bits of Lock Register 1 correspond to each of the upper sixteen 128-bit OTP Registers. Programming a bit in Lock Register 1 locks the corresponding 128-bit OTP Register. After being locked, the OTP Registers cannot be unlocked. Ordering Information Discrete Products Figure 32 Decoder for Discrete P30 TE28F640P30B8 5 Package Designator TE = 56-Lead TSOP, leaded JS = 56-Lead TSOP, lead-free RC = 64-Ball Easy BGA, leaded PC = 64-Ball Easy BGA, lead-free Product Line Designator 28F = Flash Memory Device Density 640 = 64-Mbit 128 = 128-Mbit 256 = 256-Mbit Access Speed 85 ns Parameter Location B = Bottom Parameter T = Top Parameter Product Fam ily P30 = Intel Embedded Memory VCC = V VCCQ = V Table 35 Valid Combinations for Discrete Products 64-Mbit 128-Mbit TE28F640P30B85 TE28F640P30T85 JS28F640P30B85 JS28F640P30T85 RC28F640P30B85 RC28F640P30T85 PC28F640P30B85 PC28F640P30T85 TE28F128P30B85 TE28F128P30T85 JS28F128P30B85 JS28F128P30T85 RC28F128P30B85 RC28F128P30T85 PC28F128P30B85 PC28F128P30T85 256-Mbit TE28F256P30B95 TE28F256P30T95 JS28F256P30B95 JS28F256P30T95 RC28F256P30B85 RC28F256P30T85 PC28F256P30B85 PC28F256P30T85 Datasheet 68 August 2008 306666-12 SCSP Products Figure 33 Decoder for SCSP P30 Flash #1 Flash #2 Flash #3 Flash #4 Flash Family 1/2 Flash Family 3/4 RD 4 8 F 4 0 P 0 ZBQ0 Package Designator RD = SCSP, leaded P F = SCSP, lead-free RC = 64-Ball Easy BGA, leaded PC = 64-Ball Easy BGA, lead-free TE = 56-Lead TSOP, leaded JS = 56-Lead TSOP, lead-free Group Designator 48F = Flash Memory only Flash Density 0 = No die 2 = 64-Mbit 3 = 128-M bit 4 = 256-M bit Product Family P = Intel Em bedded M em ory 0 = No die Device Details 0 = Original version of the product refer to the latest version of the datasheet for details Ballout Designator Q = QUAD+ ballout 0 = Discrete ballout Parameter, Mux Configuration B = Bottom Parameter, Non Mux T = Top Parameter, Non Mux

PDF Datasheet Preview

Numonyx StrataFlash Embedded Memory P30

Product Features

Datasheet
- High performance
- Security
85 ns initial access

One-Time Programmable Registers:
52 MHz with zero wait states, 17ns clock-to-data output
• 64 unique factory device identifier bits
synchronous-burst read mode
• 2112 user-programmable OTP bits
25 ns asynchronous-page read mode

Selectable OTP Space in Main Array:
4-, 8-, 16-, and continuous-word burst mode
• Four pre-defined 128-KByte blocks top or bottom

Buffered Enhanced Factory Programming BEFP at 5 us/
configuration
byte Typ
• Up to Full Array OTP Lockout

V buffered programming at 7 us/byte Typ

Absolute write protection VPP = VSS
- Architecture

Power-transition erase/program lockout

Individual zero-latency block locking

Multi-Level Cell Technology Highest Density at Lowest

Individual block lock-down

Cost Asymmetrically-blocked architecture
- Software

Four 32-KByte parameter blocks top or bottom
20 us Typ program suspend
configuration
20 us Typ erase suspend
128-KByte main blocks

Numonyx Flash Data Integrator optimized
- Voltage and Power

VCC core voltage V VCCQ I/O voltage V Standby current 20uA Typ for 64-Mbit

Basic Command Set and Extended Command Set compatible

Common Flash Interface capable - Density and Packaging
4-Word synchronous read current:
56- Lead TSOP package 64, 128, 256,
13 mA Typ at 40 MHz
Ordering Information Discrete SCSP

A Supplemental Reference

B Conventions - Additional Information

Datasheet 4

August 2008 306666-12

Functional Description

Introduction

This document provides information about the Numonyx Embedded Memory P30 product and describes its features, operation, and specifications.

The Numonyx Embedded Memory P30 product is the latest generation of Numonyx memory devices. Offered in 64-Mbit up through 512-Mbit densities, the P30 device brings reliable, two-bit-per-cell storage technology to the embedded flash market segment. Benefits include more density in less space, highspeed interface, lowest cost-per-bit NOR device, and support for code and data storage. Features include high-performance synchronous-burst read mode, fast asynchronous access times, low power, flexible security options, and three industry standard package choices. The P30 product family is manufactured using Intel* 130 nm ETOX VIII process technology.

The P30 product family is also planned on the Intel* 65nm process lithography. 65nm AC timing changes are noted in this datasheet, and should be taken into account for all new designs.

Overview

This section provides an overview of the features and capabilities of the P30.

The P30 family provides density upgrades from 64-Mbit through 512-Mbit. This family of devices provides high performance at low voltage on a 16-bit data bus. Individually erasable memory blocks are sized for optimum code and data storage.

Upon initial power up or return from reset, the device defaults to asynchronous pagemode read. Configuring the Read Configuration Register enables synchronous burstmode reads. In synchronous burst mode, output data is synchronized with a usersupplied clock signal. A WAIT signal provides an easy CPU-to-flash memory synchronization.

In addition to the enhanced architecture and interface, the device incorporates technology that enables fast factory program and erase operations. Designed for lowvoltage systems, the P30 supports read operations with VCC at V, and erase and program operations with VPP at V or V. Buffered Enhanced Factory Programming BEFP provides the fastest flash array programming performance with VPP at V, which increases factory throughput. With VPP at V, VCC and VPP can be tied together for a simple, ultra low power design. In addition to voltage flexibility, a dedicated VPP connection provides complete data protection when VPP VPPLK.

A Command User Interface CUI is the interface between the system processor and all internal operations of the device. An internal Write State Machine WSM automatically executes the algorithms and timings necessary for block erase and program. A Status Register indicates erase or program completion and any errors that may have occurred.

An industry-standard command sequence invokes program and erase automation. Each erase operation erases one block. The Erase Suspend feature allows system software to pause an erase cycle to read or program data in another block. Program Suspend allows system software to pause programming to read other locations. Data is programmed in word increments 16 bits .

August 2008 Order Number 306666-12

Datasheet 5

The P30 protection register allows unique flash device identification that can be used to increase system security. The individual Block Lock feature provides zero-latency block locking and unlocking. In addition, the P30 device also has four pre-defined spaces in the main array that can be configured as One-Time Programmable OTP .

Virtual Chip Enable Description

The P30 512Mbit devices employ a Virtual Chip Enable which combines two 256-Mbit die with a common chip enable, F1-CE# for QUAD+ packages or CE# for Easy BGA and TSOP packages. Refer to Figure 9 on page 21 and Figure 10 on page Address A24 Quad+ package or A25 Easy BGA and TSOP packages is then used to select between the die pair with F1-CE# / CE# asserted depending upon the package option used. When chip enable is asserted and QUAD+ A24 Easy BGA/TSOP A25 is low VIL , The lower parameter die is selected when chip enable is asserted and QUAD+ A24 Easy BGA/TSOP A25 is high VIH , the upper parameter die is selected. Refer to Table 1 and Table 2 for additional details.

Table 1 Virtual Chip Enable Truth Table for 512 Mb QUAD+ Package

Lower Param Die Upper Param Die

Die Selected

F1-CE# L

A24 L H

Table 2 Virtual Chip Enable Truth Table for 512 Mb Easy BGA & TSOP Packages

Lower Param Die Upper Param Die

Die Selected

CE# L

A25 L H

Datasheet 6

August 2008 306666-12

Memory Maps

Table 3 through Table 5 show the P30 memory maps. The memory array is divided into multiple 8-Mbit Programming Regions see Section “Program Operation” on page

Table 3 Discrete Top Parameter Memory Maps all packages

Size
64-Mbit 3FC000 -

Size

On e Programming
Table 22 Burst Sequence Word Ordering

Start Addr. DEC

Burst Wrap RCR[3]
4-Word Burst BL[2:0] = 0b001
0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2

Burst Addressing Sequence DEC
8-Word Burst BL[2:0] = 0b010
16-Word Burst BL[2:0] = 0b011
0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6

Continuous Burst BL[2:0] = 0b111
0-1-2-3 1-2-3-4 2-3-4-5 3-4-5-6
0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-8 2-3-4-5-6-7-8-9 3-4-5-6-7-8-9-10 4-5-6-7-8-9-10-11 5-6-7-8-9-10-11-12 6-7-8-9-10-11-12-13 7-8-9-10-11-12-13-
14 15

Clock Edge

The Clock Edge CE bit selects either a rising default or falling clock edge for CLK. This clock edge is used at the start of a burst cycle, to output synchronous data, and to assert/deassert WAIT.

Datasheet 46

August 2008 306666-12

Burst Wrap

The Burst Wrap BW bit determines whether 4-word, 8-word, or 16-word burst length accesses wrap within the selected word-length boundaries or cross word-length boundaries. When BW is set, burst wrapping does not occur default . When BW is cleared, burst wrapping occurs.

When performing synchronous burst reads with BW set no wrap , an output delay may occur when the burst sequence crosses its first device-row 16-word boundary. If the burst sequence’s start address is 4-word aligned, then no delay occurs. If the start address is at the end of a 4-word boundary, the worst case output delay is one clock cycle less than the first access Latency Count. This delay can take place only once, and doesn’t occur if the burst sequence does not cross a device-row boundary. WAIT informs the system of this delay when it occurs.

Burst Length

The Burst Length bit BL[2:0] selects the linear burst length for all synchronous burst reads of the flash memory array. The burst lengths are 4-word, 8-word, 16-word, and continuous word.
Continuous-burst accesses are linear only, and do not wrap within any word length boundaries see Table 22, “Burst Sequence Word Ordering” on page When a burst cycle begins, the device outputs synchronous burst data until it reaches the end of the “burstable” address space.

End of Word Line EOWL Considerations

When performing synchronous burst reads with BW set no wrap and DH reset 1 clock cycle , an output “delay” requiring additions clock Wait States may occur when the burst sequence crosses its first device-row 16-word boundary. The delay would take place only once, and will not occur if the burst sequence does not cross a device-row boundary. The WAIT signal informs the system of this delay when it occurs. If the burst sequence’s start address is 4-word aligned i.e. 0x00h, 0x04h, 0x08h, 0x0Ch then no delay occurs. If the start address is at the end of a 4-word boundary i.e. 0x03h, 0x07h, 0x0Bh, 0x0Fh , the worst case delay number of Wait States required will be one clock cycle less than the first access Latency Count LC-1 when crossing the first device-row boundary i.e. 0x0Fh to 0x10h . Other address misalignments may require wait states depending upon the LC setting and the starting address alignment. For example, an LC setting of 3 with a starting address of 0xFD requires 0 wait states, but the same LC setting of 3 with a starting address of 0xFE would require 1 wait state when crossing the first device row boundary.

One-Time-Programmable OTP Registers

The device contains 17 one-time-programmable OTP registers that can be used to implement system security measures and/or device identification. Each OTP register can be individually locked.

The first 128-bit OTP Register is comprised of two 64-bit 8-word segments. The lower 64-bit segment is pre-programmed at the Numonyx factory with a unique 64-bit number. The other 64-bit segment, as well as the other sixteen 128-bit OTP Registers, are blank. Users can program these registers as needed. When programmed, users can then lock the OTP Register s to prevent additional bit programming see Figure 16, “OTP register map” on page

The OTP Registers contain one-time programmable OTP bits when programmed, PR bits cannot be erased. Each OTP Register can be accessed multiple times to program individual bits, as long as the register remains unlocked.

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Datasheet 47

Each OTP Register has an associated Lock Register bit. When a Lock Register bit is programmed, the associated OTP Register can only be read it can no longer be programmed. Additionally, because the Lock Register bits themselves are OTP, when programmed, Lock Register bits cannot be erased. Therefore, when a OTP Register is locked, it cannot be unlocked.

Figure 16 OTP register map
0x109
128-bit Protection Register 16 User-Programmable
0x102
0x91
128-bit Protection Register 1 User-Programmable
0x8A Lock Register 1
0x89 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0x88
0x85 0x84
0x81
64-bit Segment User-Programmable
128-Bit Protection Register 0
64-bit Segment Factory-Programmed

Lock Register 0
0x80 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reading the OTP registers

The OTP registers can be read from any address. To read the OTP Register, first issue the Read Device Identifier command at any address to place the device in the Read Device Identifier state see Section “Command Set” on page Next, perform a read operation using the address offset corresponding to the register to be read. Table 13, “Device Identifier Information” on page 28 shows the address offsets of the OTP Registers and Lock Registers. PR data is read 16 bits at a time.

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Note:

Caution:

Programming the OTP Registers

To program any of the OTP Registers, first issue the Program OTP Register command at the parameter’s base address plus the offset to the desired OTP Register see Section “Command Set” on page Next, write the desired OTP Register data to the same OTP Register address see Figure 16, “OTP register map” on page

The device programs the 64-bit and 128-bit user-programmable OTP Register data 16 bits at a time see Figure 41, “Protection Register Programming Flowchart” on page Issuing the Program OTP Register command outside of the OTP Register’s address space causes a program error SR[4] set . Attempting to program a locked OTP Register causes a program error SR[4] set and a lock error SR[1] set .

When programming the OTP bits in the OTP registers for a Top Parameter Device, the following upper address bits must also be driven properly A[Max:17] driven high VIH for TSOP and Easy BGA packages, and A[Max:16] driven high VIH for QUAD+ SCSP.

Locking the OTP Registers

Each OTP Register can be locked by programming its respective lock bit in the Lock Register. To lock a OTP Register, program the corresponding bit in the Lock Register by issuing the Program Lock Register command, followed by the desired Lock Register data see Section “Command Set” on page The physical addresses of the Lock Registers are 0x80 for register 0 and 0x89 for register These addresses are used when programming the lock registers see Table 13, “Device Identifier Information” on page

Bit 0 of Lock Register 0 is already programmed during the manufacturing process at the “factory”, locking the lower, pre-programmed 64-bit region of the first 128-bit OTP Register containing the unique identification number of the device. Bit 1 of Lock Register 0 can be programmed by the user to lock the user-programmable, 64-bit region of the first 128-bit OTP Register. When programming Bit 1 of Lock Register 0, all other bits need to be left as ‘1’ such that the data programmed is 0xFFFD.

Lock Register 1 controls the locking of the upper sixteen 128-bit OTP Registers. Each of the 16 bits of Lock Register 1 correspond to each of the upper sixteen 128-bit OTP Registers. Programming a bit in Lock Register 1 locks the corresponding 128-bit OTP Register.

After being locked, the OTP Registers cannot be unlocked.
Ordering Information

Discrete Products

Figure 32 Decoder for Discrete P30 TE28F640P30B8 5

Package Designator

TE = 56-Lead TSOP, leaded JS = 56-Lead TSOP, lead-free RC = 64-Ball Easy BGA, leaded PC = 64-Ball Easy BGA, lead-free

Product Line Designator
28F = Flash Memory

Device Density
640 = 64-Mbit 128 = 128-Mbit 256 = 256-Mbit

Access Speed
85 ns

Parameter Location

B = Bottom Parameter T = Top Parameter

Product Fam ily

P30 = Intel Embedded Memory VCC = V VCCQ = V

Table 35 Valid Combinations for Discrete Products
64-Mbit
128-Mbit

TE28F640P30B85 TE28F640P30T85 JS28F640P30B85 JS28F640P30T85 RC28F640P30B85 RC28F640P30T85 PC28F640P30B85 PC28F640P30T85

TE28F128P30B85 TE28F128P30T85 JS28F128P30B85 JS28F128P30T85 RC28F128P30B85 RC28F128P30T85 PC28F128P30B85 PC28F128P30T85
256-Mbit TE28F256P30B95 TE28F256P30T95 JS28F256P30B95 JS28F256P30T95 RC28F256P30B85 RC28F256P30T85 PC28F256P30B85 PC28F256P30T85

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SCSP Products

Figure 33 Decoder for SCSP P30

Flash #1 Flash #2 Flash #3 Flash #4 Flash Family 1/2 Flash Family 3/4

RD 4 8 F 4 0 P 0 ZBQ0

Package Designator

RD = SCSP, leaded P F = SCSP, lead-free RC = 64-Ball Easy BGA, leaded PC = 64-Ball Easy BGA, lead-free TE = 56-Lead TSOP, leaded JS = 56-Lead TSOP, lead-free

Group Designator
48F = Flash Memory only

Flash Density
0 = No die 2 = 64-Mbit 3 = 128-M bit 4 = 256-M bit

Product Family

P = Intel Em bedded M em ory 0 = No die

Device Details
0 = Original version of the product refer to the latest version of the datasheet for details

Ballout Designator

Q = QUAD+ ballout 0 = Discrete ballout

Parameter, Mux Configuration

B = Bottom Parameter, Non Mux T = Top Parameter, Non Mux

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Datasheet ID: RC28F256P30B85A 648543