NP8P128AE3B1760E

NP8P128AE3B1760E Datasheet

Part Number NP8P128A13BSM60E NP8P128A13TSM60E NP8P128A13B1760E NP8P128A13T1760E

Part	Datasheet
NP8P128AE3B1760E	NP8P128AE3B1760E (pdf)

Related Parts	Information
NP8P128A13B1760E	NP8P128A13B1760E
NP8P128A13TSM60E	NP8P128A13TSM60E
NP8P128A13T1760E	NP8P128A13T1760E
NP8P128A13BSM60E	NP8P128A13BSM60E
NP8P128AE3T1760E	NP8P128AE3T1760E
NP8P128AE3TSM60E	NP8P128AE3TSM60E
NP8P128AE3BSM60E	NP8P128AE3BSM60E

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P8P Parallel Phase Change Memory PCM 128Mb P8P Parallel PCM Features • High-performance READ 115ns initial READ access 135ns initial READ access 25ns, 8-word asynchronous-page READ • Architecture Asymmetrically blocked architecture Four 32KB parameter blocks with top or bottom configuration 128KB main blocks Serial peripheral interface SPI to enable lower pin count on-board programming • Phase change memory PCM Chalcogenide phase change storage element Bit-alterable WRITE operation • Voltage and power VCC core voltage VCCQ I/O voltage Standby current 80µA TYP • Quality and reliability More than 1,000,000 WRITE cycles 90nm PCM technology • Temperature Commercial 0°C to +70°C 115ns initial READ access Industrial to +85°C 135ns initial READ access • Simplified software management No block erase or cleanup required Bit twiddle in either direction 1:0, 0:1 35µs TYP PROGRAM SUSPEND 35µs TYP ERASE SUSPEND Flash data integrator optimized Scalable command set and extended command set compatible Common Flash interface capable • Density and packaging 128Mb density 56-lead TSOP package 64-ball easy BGA package • Security One-time programmable registers 64 unique factory device identifier bits 2112 user-programmable OTP bits Selectable OTP space in main array Three adjacent main blocks available for boot code or other secure information Absolute WRITE protection VPP = VSS Power transition ERASE/PROGRAM lockout Individual zero-latency block locking Individual block lock-down Micron Technology, Inc., reserves the right to change products or specifications without notice. 2005 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 128Mb P8P Parallel PCM Table of Contents Table of Contents Features Functional Description Product Features Memory Maps Package Dimensions TSOP Mechanical Specifications 64-Ball Easy BGA Package Pinouts and Ballouts. Signal Names and Descriptions Bus Operations READ Operations WRITE Operations OUTPUT DISABLE Operations STANDBY Operations RESET Operations Command Set Device Command Codes Device Command Bus Cycles READ Operations READ ARRAY READ IDENTIFIER READ QUERY PROGRAM Operations WORD PROGRAM BIT-ALTERABLE WORD WRITE BUFFERED PROGRAM BIT-ALTERABLE BUFFER WRITE. BIT-ALTERABLE BUFFER PROGRAM SUSPEND PROGRAM RESUME PROGRAM PROTECTION. ERASE. BLOCK ERASE SUSPEND ERASE RESUME Security Mode Block Locking Zero Latency Block Locking Lock Block Unlock Block Lock Down Block WP# Lock Down Control. Block Lock Status Locking Operations During ERASE SUSPEND. Permanent OTP Block Locking WP# Lock Down Control for Selectable OTP Lock Blocks Selectable OTP Locking Implementation Details Registers Read Status Register. CLEAR STATUS REGISTER Command System Protection Registers Micron Technology, Inc., reserves the right to change products or specifications without notice. 2005 Micron Technology, Inc. All rights reserved. 128Mb P8P Parallel PCM Table of Contents Read Protection Register. Program Protection Register Lock Protection Register OTP Protection Register Addressing Details Serial Peripheral Interface SPI Overview SPI Signal Names SPI Memory Organization SPI Instruction WRITE ENABLE WREN . WRITE DISABLE WRDI . READ IDENTIFICATION RDID Read Status Register RDSR WIP Bit WEL Bit BP3, BP2, BP1, BP0 Bits Top/Bottom Bit. SRWD Bit WRITE STATUS REGISTER WRSR Read Data Bytes READ Data Bytes at Higher Speed FAST_READ PAGE PROGRAM PP SECTOR ERASE SE Power and Reset Specification Power-Up and Power-Down Reset Specifications Power Supply Decoupling Maximum Ratings and Operating Conditions Absolute Maximum Ratings Operating Conditions Endurance Electrical Specifications. DC Current Characteristics DC Voltage Characteristics. AC Characteristics AC Test Conditions Capacitance AC Read Specifications AC Write Specifications. SPI AC Specifications. Program and Erase Characteristics Ordering Information. Supplemental Reference Information Flowcharts Write State Machine Common Flash Interface Query Structure Output Query Structure Overview CFI Query Identification String Extended Query Tables Micron Technology, Inc., reserves the right to change products or specifications without notice. 2005 Micron Technology, Inc. All rights reserved. 128Mb P8P Parallel PCM List of Figures List of Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 Figure 37 Figure 38 Figure 39 Figure 40: 56-Lead TSOP 64-Ball Easy BGA Package 56-Lead TSOP Pinout 128Mb 64-Ball Easy BGA Ballout 128Mb Example VPP Power Supply Configuration. Block Locking State Diagram Selectable OTP Locking Illustration Bottom Parameter Device Example Protection Register Memory Map WRITE ENABLE WREN Instruction Sequence. WRITE DISABLE WRDI Instruction Sequence READ IDENTIFICATION RDID Instruction Sequence and Data-Out Sequence READ STATUS REGISTER RDSR Instruction Sequence and Data-Out Sequence WRITE STATUS REGISTER WRSR Instruction Sequence Read Data Bytes READ Instruction Sequence and Data-Out Sequence FAST_READ Instruction Sequence and Data-Out Sequence PAGE PROGRAM PP Instruction Sequence SECTOR ERASE SE Instruction Sequence Reset Operation Waveforms. AC Input/Output Reference Waveform Transient Equivalent Testing Load Circuit Asynchronous Single-Word Read Asynchronous Page Mode Read Timing Write-to-Write Timing Asynchronous Read to Write Timing Write to Asynchronous Read Timing Serial Input Timing. Write Protect Setup and Hold Timing during WRSR when SRWD = 1 Hold Timing Output Timing. WORD PROGRAM or BIT-ALTERABLE WORD WRITE Flowchart. Full WRITE STATUS CHECK Flowchart. WRITE SUSPEND/RESUME Flowchart BUFFER PROGRAM or Bit-Alterable BUFFER WRITE Flowchart BLOCK ERASE Flowchart BLOCK ERASE FULL ERASE STATUS CHECK Flowchart ERASE SUSPEND/RESUME Flowchart LOCKING OPERATIONS Flowchart PROGRAM PROTECTION REGISTER Flowchart FULL STATUS CHECK Flowchart Write State Machine Next State Table. Micron Technology, Inc., reserves the right to change products or specifications without notice. 2005 Micron Technology, Inc. All rights reserved. 128Mb P8P Parallel PCM List of Tables List of Tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Table 32 Table 33 Table 34 Table 35 Table 36 Table 37 Table 38 Table 39 Table 40 Table 41 Table 42 Table 43 Table 44 Table 45 Table 46 Table 47 Table 48 Table 49 Table 50 Table 51: Top Parameter Memory Map. Bottom Parameter Memory Map TSOP Package Dimensions. Easy BGA Package Dimensions Ball/Pin Descriptions. Bus Operations Command Codes and Descriptions Command Sequences in x16 Bus Mode. Read Identifier Table Device Codes Buffered Programming and Bit-Alterable Buffer Write Timing Requirements Bit Alterability vs. Flash Bit-Masking Block Locking Truth Table Block Locking State Transitions Selectable OTP Block Locking Feature. Selectable OTP Block Locking Programming of PR-LOCK0 Status Register Definitions Protection Register Addressing 2K OTP Space Addressing Memory Organization Instruction Set Status Register Format. Protected Area Sizes Power and Reset Absolute Maximum Ratings Operating Conditions Endurance DC Current Characteristics. DC Voltage Characteristics Test Configuration Component Value for Worst-Case Speed Conditions Capacitance TA = 25°C, f = 1 MHz1 AC Read Specifications AC Write Characteristics SPI AC Specifications Program and Erase Specifications. Active Line Item Ordering Table 0°C to 70°C Active Line Item Ordering Table to 85°C WORD PROGRAM or BIT-ALTERABLE WORD WRITE Procedure Full WRITE STATUS CHECK Procedure WRITE SUSPEND/RESUME Procedure. BUFFER PROGRAM OR BIT-ALTERABLE BUFFER WRITE Procedure. BLOCK ERASE Procedure BLOCK ERASE FULL ERASE STATUS CHECK Procedure ERASE SUSPEND/RESUME Procedure LOCKING OPERATIONS Procedure PROGRAM PROTECTION REGISTER Procedure. FULL STATUS CHECK Procedure Summary of Query Structure Output as a Function of Device and Model Example of Query Structure Output of x16 Devices Query Structure. Block Status Register Micron Technology, Inc., reserves the right to change products or specifications without notice. 2005 Micron Technology, Inc. All rights reserved. 128Mb P8P Parallel PCM List of Tables Table 52 Table 53 Table 54 Table 55 Table 56 Table 57 Table 58 Table 59 Table 60 Table 61: CFI Identification System Interface Information Device Geometry Definition. Bit Field Definitions Hex Code and Values for Device Geometry Primary Vendor-Specific Extended Query Protection Register Information Read Information Partition and Erase Block Region Information. Hex Code and Values for Partition and Erase Block Regions Micron Technology, Inc., reserves the right to change products or specifications without notice. 2005 Micron Technology, Inc. All rights reserved. 128Mb P8P Parallel PCM Functional Description Functional Description Unlike other proposed alternative memories, P8P parallel PCM technology uses a conventional CMOS process with the addition of a few additional layers to form the memory storage element. Overall, the basic memory manufacturing process used to make PCM is less complex than that of NAND, NOR or DRAM. P8P parallel PCM combines the benefits of traditional floating gate Flash, both NORtype and NAND-type, with some of the key attributes of RAM and EEPROM. Like NOR Flash and RAM technology, PCM offers fast random access times. Like NAND flash, PCM has the ability to write moderately fast, and like RAM and EEPROM, PCM supports bit alterable WRITEs overwrite . Unlike Flash, no separate erase step is required to change information from 0 to 1 and 1 to Unlike RAM, however, the technology is nonvolatile with data retention compared with NOR Flash. Product Features P8P parallel PCM devices provide the convenience and ease of NOR flash emulation while providing a set of super set features that exploit the inherent capabilities of PCM technology. The device emulates most of the features of Micron embedded memory P33 . This is intended to ease the evaluation and design of P8P parallel PCM into existing hardware and software development platforms. This basic features set is supplemented by the super set features, which are intended to enable the designer to exploit the inherent capabilities of phase change memory technology and to enable the eventual simplification of hardware and software in the design. The P8P parallel PCM product family supports 128Mb density and are available in 64ball easy BGA and 56-lead TSOP packages. These are the same pinouts and packages as the existing P33 NOR Flash devices. Designed for low -oltage systems, P8P parallel PCM supports READ, WRITE, and ERASE operations at a core supply of 2.7V VCC. P8P parallel PCM offers additional power savings through standby mode, which is initiated when the system deselects the device by driving CE inactive. P8P parallel PCM provides a set of commands that are compatible with industry-standard command sequences used by NOR-type Flash. An internal write state machine WSM automatically executes the algorithms and timings necessary for BLOCK ERASE and WRITE. Each emulated BLOCK ERASE operation results in the contents of the addressed block being written to all 1s. Data can be programmed in word or buffer increments. Erase suspend enables system software to pause an ERASE command so it can Micron Technology, Inc., reserves the right to change products or specifications without notice. 2005 Micron Technology, Inc. All rights reserved. 128Mb P8P Parallel PCM Memory Maps read or program data in another block. PROGRAM SUSPEND enables system software to pause programming so it can read from other locations within the device. The status register indicates when the WSM’s BLOCK ERASE or PROGRAM operation is finished. A 64-byte, 32 word write buffer is also included to enable optimum write performance. Using the write buffer, data is overwritten or programmed in buffer increments. This feature improves system program performance more than 20 times over independent byte writes. Similar to floating gate Flash, a command user interface CUI serves as the interface between the system processor and internal operation of the device. A valid command sequence written to the CUI initiates device automation. In addition to the CUI, a Flashcompatible common Flash interface CFI permits software algorithms to be used for entire families of devices. This enables device-independent, JEDEC ID-independent, and forward- and backward-compatible software support for the specified Flash device families. The serial peripheral interface SPI enables in-system programming through minimal pin count interface. This interface is provided in addition to a traditional parallel system interface. This feature has been added to facilitate the on-board, in-system programming of code into the P8P parallel PCM device after it has been soldered to a circuit board. Preprogramming code prior to high temperature board attach is not recommended with a P8P parallel PCM device. Although device reliability across the operating temperature range is typically superior to that of floating gate Flash, the P8P parallel PCM device may be subject to thermally-activated disturbs at higher temperatures however, no permanent device damage occurs either during leaded or lead-free board attach. P8P parallel PCM block locking enables zero-latency block locking/unlocking and permanent locking. Permanent block locking provides enhanced security for boot code. The combination of these two locking features provides complete locking solution for code and data. PCM technology also supports the ability to change each memory bit independently from 0 to 1 or 1 to 0 without an intervening BLOCK ERASE operation. Bit alterability enables software to write to the nonvolatile memory in a similar manner as writing to RAM or EEPROM without the overhead of erasing blocks prior to write. Bit Alterable writes use similar command sequences as word programming and Buffer Programming. Memory Maps Table 1 Top Parameter Memory Map Programming Region Number 7 Size KW 16 64 Block 130 129 128 127 126 128Mb 7F8000-7FBFFF 7F4000-7F7FFF 7F0000-7F3FFF 7E0000-7EFFFF Micron Technology, Inc., reserves the right to change products or specifications without notice. 2005 Micron Technology, Inc. All rights reserved. Table 1 Top Parameter Memory Map Continued Programming Region Number 5 Size KW 64 Block 95 Table 2 Bottom Parameter Memory Map Programming Region Number 7 Size KW 64 Block 130 128Mb P8P Parallel PCM Memory Maps 128Mb P8P Parallel PCM Ordering Information These performance numbers are valid for all speed versions. Sampled, not 100% tested. Ordering Information Table 36 Active Line Item Ordering Table 0°C to 70°C Part Number NP8P128A13BSM60E NP8P128A13TSM60E NP8P128A13B1760E NP8P128A13T1760E P8P 128Mb TSOP 14 x 20 Bottom Boot P8P 128Mb TSOP 14 x 20 Top Boot P8P 128M lead-free 10 x 8 x easy BGA Bottom Boot P8P 128M lead-free 10 x 8 x easy BGA Top Boot Table 37 Active Line Item Ordering Table to 85°C Part Number NP8P128AE3BSM60E NP8P128AE3TSM60E NP8P128AE3B1760E NP8P128AE3T1760E P8P 128Mb TSOP 14 x 20 Bottom Boot P8P 128Mb TSOP 14 x 20 Top Boot P8P 128M lead-free 10 x 8 x easy BGA Bottom Boot P8P 128M lead-free 10 x 8 x easy BGA Top Boot Micron Technology, Inc., reserves the right to change products or specifications without notice. 2005 Micron Technology, Inc. All rights reserved. 128Mb P8P Parallel PCM Supplemental Reference Information Supplemental Reference Information Flowcharts Figure 30 WORD PROGRAM or BIT-ALTERABLE WORD WRITE Flowchart Start Write 40h or 42h Program word address setup Write data word address Confirm data Read status register 0 SR7 = 1 Full status check if desired Suspend write Suspend write loop Write complete Table 38 WORD PROGRAM or BIT-ALTERABLE WORD WRITE Procedure Bus Operation WRITE WRITE READ Standby Command PROGRAM/WRITE SETUP DATA Notes Data = 40h or 42h bit alterable Addr = Location to WRITE WA Data = Data to be written WD Addr = Location to be written WA Status register data initiate a READ cycle to update status register Check SR7 1 = WSM ready 0 = WSM busy Repeat for subsequent WRITE operations Full status register check can be done after each WRITE or after a sequence of WRITE opera- tions. Micron Technology, Inc., reserves the right to change products or specifications without notice. 2005 Micron Technology, Inc. All rights reserved. 128Mb P8P Parallel PCM Supplemental Reference Information WRITE FFh after the last operation to end read array mode. Figure 31 Full WRITE STATUS CHECK Flowchart Read status register 1 SR3 = 1 SR4 = 1 SR1 = 0 Write successful VPP range error Write error Device protect error Table 39 Full WRITE STATUS CHECK Procedure

PDF Datasheet Preview

P8P Parallel Phase Change Memory PCM
128Mb P8P Parallel PCM Features
• High-performance READ 115ns initial READ access 135ns initial READ access 25ns, 8-word asynchronous-page READ
• Architecture Asymmetrically blocked architecture Four 32KB parameter blocks with top or bottom configuration 128KB main blocks Serial peripheral interface SPI to enable lower pin count on-board programming
• Phase change memory PCM Chalcogenide phase change storage element Bit-alterable WRITE operation
• Voltage and power VCC core voltage VCCQ I/O voltage Standby current 80µA TYP
• Quality and reliability More than 1,000,000 WRITE cycles 90nm PCM technology
• Temperature Commercial 0°C to +70°C 115ns initial READ access Industrial to +85°C 135ns initial READ access
• Simplified software management No block erase or cleanup required Bit twiddle in either direction 1:0, 0:1 35µs TYP PROGRAM SUSPEND 35µs TYP ERASE SUSPEND Flash data integrator optimized Scalable command set and extended command set compatible Common Flash interface capable
• Density and packaging 128Mb density 56-lead TSOP package 64-ball easy BGA package
• Security One-time programmable registers 64 unique factory device identifier bits 2112 user-programmable OTP bits Selectable OTP space in main array Three adjacent main blocks available for boot code or other secure information Absolute WRITE protection VPP = VSS Power transition ERASE/PROGRAM lockout Individual zero-latency block locking Individual block lock-down

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2005 Micron Technology, Inc. All rights reserved.

Products and specifications discussed herein are subject to change by Micron without notice.
128Mb P8P Parallel PCM Table of Contents

Table of Contents

Features Functional Description Product Features Memory Maps Package Dimensions

TSOP Mechanical Specifications 64-Ball Easy BGA Package Pinouts and Ballouts. Signal Names and Descriptions Bus Operations READ Operations WRITE Operations OUTPUT DISABLE Operations STANDBY Operations RESET Operations Command Set Device Command Codes Device Command Bus Cycles READ Operations READ ARRAY READ IDENTIFIER READ QUERY PROGRAM Operations WORD PROGRAM BIT-ALTERABLE WORD WRITE BUFFERED PROGRAM BIT-ALTERABLE BUFFER WRITE. BIT-ALTERABLE BUFFER PROGRAM SUSPEND PROGRAM RESUME PROGRAM PROTECTION. ERASE. BLOCK ERASE SUSPEND ERASE RESUME Security Mode Block Locking Zero Latency Block Locking Lock Block Unlock Block Lock Down Block WP# Lock Down Control. Block Lock Status Locking Operations During ERASE SUSPEND. Permanent OTP Block Locking WP# Lock Down Control for Selectable OTP Lock Blocks Selectable OTP Locking Implementation Details Registers Read Status Register. CLEAR STATUS REGISTER Command System Protection Registers

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2005 Micron Technology, Inc. All rights reserved.
128Mb P8P Parallel PCM Table of Contents
Read Protection Register. Program Protection Register Lock Protection Register OTP Protection Register Addressing Details Serial Peripheral Interface SPI Overview SPI Signal Names SPI Memory Organization SPI Instruction WRITE ENABLE WREN . WRITE DISABLE WRDI . READ IDENTIFICATION RDID Read Status Register RDSR WIP Bit WEL Bit BP3, BP2, BP1, BP0 Bits Top/Bottom Bit. SRWD Bit WRITE STATUS REGISTER WRSR Read Data Bytes READ Data Bytes at Higher Speed FAST_READ PAGE PROGRAM PP SECTOR ERASE SE Power and Reset Specification Power-Up and Power-Down Reset Specifications Power Supply Decoupling Maximum Ratings and Operating Conditions Absolute Maximum Ratings Operating Conditions Endurance Electrical Specifications. DC Current Characteristics DC Voltage Characteristics. AC Characteristics AC Test Conditions Capacitance AC Read Specifications AC Write Specifications. SPI AC Specifications. Program and Erase Characteristics Ordering Information. Supplemental Reference Information Flowcharts Write State Machine Common Flash Interface Query Structure Output Query Structure Overview CFI Query Identification String Extended Query Tables

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2005 Micron Technology, Inc. All rights reserved.
128Mb P8P Parallel PCM List of Figures

List of Figures

Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 Figure 37 Figure 38 Figure 39 Figure 40:
56-Lead TSOP 64-Ball Easy BGA Package 56-Lead TSOP Pinout 128Mb 64-Ball Easy BGA Ballout 128Mb Example VPP Power Supply Configuration. Block Locking State Diagram Selectable OTP Locking Illustration Bottom Parameter Device Example Protection Register Memory Map WRITE ENABLE WREN Instruction Sequence. WRITE DISABLE WRDI Instruction Sequence READ IDENTIFICATION RDID Instruction Sequence and Data-Out Sequence READ STATUS REGISTER RDSR Instruction Sequence and Data-Out Sequence WRITE STATUS REGISTER WRSR Instruction Sequence Read Data Bytes READ Instruction Sequence and Data-Out Sequence FAST_READ Instruction Sequence and Data-Out Sequence PAGE PROGRAM PP Instruction Sequence SECTOR ERASE SE Instruction Sequence Reset Operation Waveforms. AC Input/Output Reference Waveform Transient Equivalent Testing Load Circuit Asynchronous Single-Word Read Asynchronous Page Mode Read Timing Write-to-Write Timing Asynchronous Read to Write Timing Write to Asynchronous Read Timing Serial Input Timing. Write Protect Setup and Hold Timing during WRSR when SRWD = 1 Hold Timing Output Timing. WORD PROGRAM or BIT-ALTERABLE WORD WRITE Flowchart. Full WRITE STATUS CHECK Flowchart. WRITE SUSPEND/RESUME Flowchart BUFFER PROGRAM or Bit-Alterable BUFFER WRITE Flowchart BLOCK ERASE Flowchart BLOCK ERASE FULL ERASE STATUS CHECK Flowchart ERASE SUSPEND/RESUME Flowchart LOCKING OPERATIONS Flowchart PROGRAM PROTECTION REGISTER Flowchart FULL STATUS CHECK Flowchart Write State Machine Next State Table.

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2005 Micron Technology, Inc. All rights reserved.
128Mb P8P Parallel PCM List of Tables

List of Tables

Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Table 32 Table 33 Table 34 Table 35 Table 36 Table 37 Table 38 Table 39 Table 40 Table 41 Table 42 Table 43 Table 44 Table 45 Table 46 Table 47 Table 48 Table 49 Table 50 Table 51:
Top Parameter Memory Map. Bottom Parameter Memory Map TSOP Package Dimensions. Easy BGA Package Dimensions Ball/Pin Descriptions. Bus Operations Command Codes and Descriptions Command Sequences in x16 Bus Mode. Read Identifier Table Device Codes Buffered Programming and Bit-Alterable Buffer Write Timing Requirements Bit Alterability vs. Flash Bit-Masking Block Locking Truth Table Block Locking State Transitions Selectable OTP Block Locking Feature. Selectable OTP Block Locking Programming of PR-LOCK0 Status Register Definitions Protection Register Addressing 2K OTP Space Addressing Memory Organization Instruction Set Status Register Format. Protected Area Sizes Power and Reset Absolute Maximum Ratings Operating Conditions Endurance DC Current Characteristics. DC Voltage Characteristics Test Configuration Component Value for Worst-Case Speed Conditions Capacitance TA = 25°C, f = 1 MHz1 AC Read Specifications AC Write Characteristics SPI AC Specifications Program and Erase Specifications. Active Line Item Ordering Table 0°C to 70°C Active Line Item Ordering Table to 85°C WORD PROGRAM or BIT-ALTERABLE WORD WRITE Procedure Full WRITE STATUS CHECK Procedure WRITE SUSPEND/RESUME Procedure. BUFFER PROGRAM OR BIT-ALTERABLE BUFFER WRITE Procedure. BLOCK ERASE Procedure BLOCK ERASE FULL ERASE STATUS CHECK Procedure ERASE SUSPEND/RESUME Procedure LOCKING OPERATIONS Procedure PROGRAM PROTECTION REGISTER Procedure. FULL STATUS CHECK Procedure Summary of Query Structure Output as a Function of Device and Model Example of Query Structure Output of x16 Devices Query Structure. Block Status Register

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2005 Micron Technology, Inc. All rights reserved.
128Mb P8P Parallel PCM List of Tables

Table 52 Table 53 Table 54 Table 55 Table 56 Table 57 Table 58 Table 59 Table 60 Table 61:

CFI Identification System Interface Information Device Geometry Definition. Bit Field Definitions Hex Code and Values for Device Geometry Primary Vendor-Specific Extended Query Protection Register Information Read Information Partition and Erase Block Region Information. Hex Code and Values for Partition and Erase Block Regions

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2005 Micron Technology, Inc. All rights reserved.
128Mb P8P Parallel PCM Functional Description

Functional Description

Unlike other proposed alternative memories, P8P parallel PCM technology uses a conventional CMOS process with the addition of a few additional layers to form the memory storage element. Overall, the basic memory manufacturing process used to make PCM is less complex than that of NAND, NOR or DRAM.

P8P parallel PCM combines the benefits of traditional floating gate Flash, both NORtype and NAND-type, with some of the key attributes of RAM and EEPROM. Like NOR Flash and RAM technology, PCM offers fast random access times. Like NAND flash, PCM has the ability to write moderately fast, and like RAM and EEPROM, PCM supports bit alterable WRITEs overwrite . Unlike Flash, no separate erase step is required to change information from 0 to 1 and 1 to Unlike RAM, however, the technology is nonvolatile with data retention compared with NOR Flash.

Product Features

P8P parallel PCM devices provide the convenience and ease of NOR flash emulation while providing a set of super set features that exploit the inherent capabilities of PCM technology. The device emulates most of the features of Micron embedded memory P33 . This is intended to ease the evaluation and design of P8P parallel PCM into existing hardware and software development platforms. This basic features set is supplemented by the super set features, which are intended to enable the designer to exploit the inherent capabilities of phase change memory technology and to enable the eventual simplification of hardware and software in the design.

The P8P parallel PCM product family supports 128Mb density and are available in 64ball easy BGA and 56-lead TSOP packages. These are the same pinouts and packages as the existing P33 NOR Flash devices. Designed for low -oltage systems, P8P parallel PCM supports READ, WRITE, and ERASE operations at a core supply of 2.7V VCC. P8P parallel PCM offers additional power savings through standby mode, which is initiated when the system deselects the device by driving CE inactive.

P8P parallel PCM provides a set of commands that are compatible with industry-standard command sequences used by NOR-type Flash. An internal write state machine WSM automatically executes the algorithms and timings necessary for BLOCK ERASE and WRITE. Each emulated BLOCK ERASE operation results in the contents of the addressed block being written to all 1s. Data can be programmed in word or buffer increments. Erase suspend enables system software to pause an ERASE command so it can

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2005 Micron Technology, Inc. All rights reserved.
128Mb P8P Parallel PCM Memory Maps
read or program data in another block. PROGRAM SUSPEND enables system software to pause programming so it can read from other locations within the device. The status register indicates when the WSM’s BLOCK ERASE or PROGRAM operation is finished.

A 64-byte, 32 word write buffer is also included to enable optimum write performance. Using the write buffer, data is overwritten or programmed in buffer increments. This feature improves system program performance more than 20 times over independent byte writes.

Similar to floating gate Flash, a command user interface CUI serves as the interface between the system processor and internal operation of the device. A valid command sequence written to the CUI initiates device automation. In addition to the CUI, a Flashcompatible common Flash interface CFI permits software algorithms to be used for entire families of devices. This enables device-independent, JEDEC ID-independent, and forward- and backward-compatible software support for the specified Flash device families.

The serial peripheral interface SPI enables in-system programming through minimal pin count interface. This interface is provided in addition to a traditional parallel system interface. This feature has been added to facilitate the on-board, in-system programming of code into the P8P parallel PCM device after it has been soldered to a circuit board. Preprogramming code prior to high temperature board attach is not recommended with a P8P parallel PCM device. Although device reliability across the operating temperature range is typically superior to that of floating gate Flash, the P8P parallel PCM device may be subject to thermally-activated disturbs at higher temperatures however, no permanent device damage occurs either during leaded or lead-free board attach.

P8P parallel PCM block locking enables zero-latency block locking/unlocking and permanent locking. Permanent block locking provides enhanced security for boot code. The combination of these two locking features provides complete locking solution for code and data.

PCM technology also supports the ability to change each memory bit independently from 0 to 1 or 1 to 0 without an intervening BLOCK ERASE operation. Bit alterability enables software to write to the nonvolatile memory in a similar manner as writing to RAM or EEPROM without the overhead of erasing blocks prior to write. Bit Alterable writes use similar command sequences as word programming and Buffer Programming.

Memory Maps

Table 1 Top Parameter Memory Map

Programming Region Number 7

Size KW
16 64

Block
130 129 128 127 126
128Mb
7F8000-7FBFFF 7F4000-7F7FFF 7F0000-7F3FFF 7E0000-7EFFFF

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2005 Micron Technology, Inc. All rights reserved.

Table 1 Top Parameter Memory Map Continued

Programming Region Number 5

Size KW 64

Block 95

Table 2 Bottom Parameter Memory Map

Programming Region Number 7

Size KW 64

Block 130
128Mb P8P Parallel PCM Memory Maps
128Mb P8P Parallel PCM Ordering Information

These performance numbers are valid for all speed versions. Sampled, not 100% tested.
Ordering Information
Table 36 Active Line Item Ordering Table 0°C to 70°C

Part Number NP8P128A13BSM60E NP8P128A13TSM60E NP8P128A13B1760E NP8P128A13T1760E

P8P 128Mb TSOP 14 x 20 Bottom Boot P8P 128Mb TSOP 14 x 20 Top Boot P8P 128M lead-free 10 x 8 x easy BGA Bottom Boot P8P 128M lead-free 10 x 8 x easy BGA Top Boot
Table 37 Active Line Item Ordering Table to 85°C

Part Number NP8P128AE3BSM60E NP8P128AE3TSM60E NP8P128AE3B1760E NP8P128AE3T1760E

P8P 128Mb TSOP 14 x 20 Bottom Boot P8P 128Mb TSOP 14 x 20 Top Boot P8P 128M lead-free 10 x 8 x easy BGA Bottom Boot P8P 128M lead-free 10 x 8 x easy BGA Top Boot

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2005 Micron Technology, Inc. All rights reserved.
128Mb P8P Parallel PCM Supplemental Reference Information

Supplemental Reference Information

Flowcharts

Figure 30 WORD PROGRAM or BIT-ALTERABLE WORD WRITE Flowchart

Start

Write 40h or 42h Program word address setup

Write data word address

Confirm data

Read status register
0 SR7 =
1 Full status check
if desired

Suspend write

Suspend write loop

Write complete

Table 38 WORD PROGRAM or BIT-ALTERABLE WORD WRITE Procedure

Bus Operation WRITE

WRITE

READ Standby

Command

PROGRAM/WRITE SETUP DATA

Notes

Data = 40h or 42h bit alterable Addr = Location to WRITE WA Data = Data to be written WD Addr = Location to be written WA Status register data initiate a READ cycle to update status register Check SR7 1 = WSM ready 0 = WSM busy

Repeat for subsequent WRITE operations Full status register check can be done after each WRITE or after a sequence of WRITE opera-
tions.

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2005 Micron Technology, Inc. All rights reserved.
128Mb P8P Parallel PCM Supplemental Reference Information

WRITE FFh after the last operation to end read array mode. Figure 31 Full WRITE STATUS CHECK Flowchart

Read status register
1 SR3 =
1 SR4 =
1 SR1 =
0 Write successful

VPP range error

Write error

Device protect error

Table 39 Full WRITE STATUS CHECK Procedure

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Datasheet ID: NP8P128AE3B1760E 648542